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<title>nativeGen/Alpha/RegInfo.hs</title>
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<pre><a name="line-1"></a>
<a name="line-2"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span>
<a name="line-3"></a><span class='hs-comment'>--</span>
<a name="line-4"></a><span class='hs-comment'>-- (c) The University of Glasgow 1996-2004</span>
<a name="line-5"></a><span class='hs-comment'>--</span>
<a name="line-6"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span>
<a name="line-7"></a>
<a name="line-8"></a><span class='hs-keyword'>module</span> <span class='hs-conid'>Alpha</span><span class='hs-varop'>.</span><span class='hs-conid'>RegInfo</span> <span class='hs-layout'>(</span>
<a name="line-9"></a><span class='hs-comment'>{-
<a name="line-10"></a> RegUsage(..),
<a name="line-11"></a> noUsage,
<a name="line-12"></a> regUsage,
<a name="line-13"></a> patchRegs,
<a name="line-14"></a> jumpDests,
<a name="line-15"></a> isJumpish,
<a name="line-16"></a> patchJump,
<a name="line-17"></a> isRegRegMove,
<a name="line-18"></a>
<a name="line-19"></a> JumpDest, canShortcut, shortcutJump, shortcutStatic,
<a name="line-20"></a>
<a name="line-21"></a> maxSpillSlots,
<a name="line-22"></a> mkSpillInstr,
<a name="line-23"></a> mkLoadInstr,
<a name="line-24"></a> mkRegRegMoveInstr,
<a name="line-25"></a> mkBranchInstr
<a name="line-26"></a>-}</span>
<a name="line-27"></a><span class='hs-layout'>)</span>
<a name="line-28"></a>
<a name="line-29"></a><span class='hs-keyword'>where</span>
<a name="line-30"></a>
<a name="line-31"></a><span class='hs-comment'>{-
<a name="line-32"></a>#include "nativeGen/NCG.h"
<a name="line-33"></a>#include "HsVersions.h"
<a name="line-34"></a>
<a name="line-35"></a>
<a name="line-36"></a>import BlockId
<a name="line-37"></a>import Cmm
<a name="line-38"></a>import CLabel
<a name="line-39"></a>import Instrs
<a name="line-40"></a>import Regs
<a name="line-41"></a>import Outputable
<a name="line-42"></a>import Constants ( rESERVED_C_STACK_BYTES )
<a name="line-43"></a>import FastBool
<a name="line-44"></a>
<a name="line-45"></a>data RegUsage = RU [Reg] [Reg]
<a name="line-46"></a>
<a name="line-47"></a>noUsage :: RegUsage
<a name="line-48"></a>noUsage = RU [] []
<a name="line-49"></a>
<a name="line-50"></a>regUsage :: Instr -> RegUsage
<a name="line-51"></a>
<a name="line-52"></a>regUsage instr = case instr of
<a name="line-53"></a> SPILL reg slot -> usage ([reg], [])
<a name="line-54"></a> RELOAD slot reg -> usage ([], [reg])
<a name="line-55"></a> LD B reg addr -> usage (regAddr addr, [reg, t9])
<a name="line-56"></a> LD Bu reg addr -> usage (regAddr addr, [reg, t9])
<a name="line-57"></a>-- LD W reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
<a name="line-58"></a>-- LD Wu reg addr -> usage (regAddr addr, [reg, t9]) : UNUSED
<a name="line-59"></a> LD sz reg addr -> usage (regAddr addr, [reg])
<a name="line-60"></a> LDA reg addr -> usage (regAddr addr, [reg])
<a name="line-61"></a> LDAH reg addr -> usage (regAddr addr, [reg])
<a name="line-62"></a> LDGP reg addr -> usage (regAddr addr, [reg])
<a name="line-63"></a> LDI sz reg imm -> usage ([], [reg])
<a name="line-64"></a> ST B reg addr -> usage (reg : regAddr addr, [t9, t10])
<a name="line-65"></a>-- ST W reg addr -> usage (reg : regAddr addr, [t9, t10]) : UNUSED
<a name="line-66"></a> ST sz reg addr -> usage (reg : regAddr addr, [])
<a name="line-67"></a> CLR reg -> usage ([], [reg])
<a name="line-68"></a> ABS sz ri reg -> usage (regRI ri, [reg])
<a name="line-69"></a> NEG sz ov ri reg -> usage (regRI ri, [reg])
<a name="line-70"></a> ADD sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-71"></a> SADD sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-72"></a> SUB sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-73"></a> SSUB sz sc r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-74"></a> MUL sz ov r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-75"></a> DIV sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
<a name="line-76"></a> REM sz un r1 ar r2 -> usage (r1 : regRI ar, [r2, t9, t10, t11, t12])
<a name="line-77"></a> NOT ri reg -> usage (regRI ri, [reg])
<a name="line-78"></a> AND r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-79"></a> ANDNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-80"></a> OR r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-81"></a> ORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-82"></a> XOR r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-83"></a> XORNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-84"></a> SLL r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-85"></a> SRL r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-86"></a> SRA r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-87"></a> ZAP r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-88"></a> ZAPNOT r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-89"></a> CMP co r1 ar r2 -> usage (r1 : regRI ar, [r2])
<a name="line-90"></a> FCLR reg -> usage ([], [reg])
<a name="line-91"></a> FABS r1 r2 -> usage ([r1], [r2])
<a name="line-92"></a> FNEG sz r1 r2 -> usage ([r1], [r2])
<a name="line-93"></a> FADD sz r1 r2 r3 -> usage ([r1, r2], [r3])
<a name="line-94"></a> FDIV sz r1 r2 r3 -> usage ([r1, r2], [r3])
<a name="line-95"></a> FMUL sz r1 r2 r3 -> usage ([r1, r2], [r3])
<a name="line-96"></a> FSUB sz r1 r2 r3 -> usage ([r1, r2], [r3])
<a name="line-97"></a> CVTxy sz1 sz2 r1 r2 -> usage ([r1], [r2])
<a name="line-98"></a> FCMP sz co r1 r2 r3 -> usage ([r1, r2], [r3])
<a name="line-99"></a> FMOV r1 r2 -> usage ([r1], [r2])
<a name="line-100"></a>
<a name="line-101"></a>
<a name="line-102"></a> -- We assume that all local jumps will be BI/BF/BR. JMP must be out-of-line.
<a name="line-103"></a> BI cond reg lbl -> usage ([reg], [])
<a name="line-104"></a> BF cond reg lbl -> usage ([reg], [])
<a name="line-105"></a> JMP reg addr hint -> RU (mkRegSet (filter interesting (regAddr addr))) freeRegSet
<a name="line-106"></a>
<a name="line-107"></a> BSR _ n -> RU (argRegSet n) callClobberedRegSet
<a name="line-108"></a> JSR reg addr n -> RU (argRegSet n) callClobberedRegSet
<a name="line-109"></a>
<a name="line-110"></a> _ -> noUsage
<a name="line-111"></a>
<a name="line-112"></a> where
<a name="line-113"></a> usage (src, dst) = RU (mkRegSet (filter interesting src))
<a name="line-114"></a> (mkRegSet (filter interesting dst))
<a name="line-115"></a>
<a name="line-116"></a> interesting (FixedReg _) = False
<a name="line-117"></a> interesting _ = True
<a name="line-118"></a>
<a name="line-119"></a> regAddr (AddrReg r1) = [r1]
<a name="line-120"></a> regAddr (AddrRegImm r1 _) = [r1]
<a name="line-121"></a> regAddr (AddrImm _) = []
<a name="line-122"></a>
<a name="line-123"></a> regRI (RIReg r) = [r]
<a name="line-124"></a> regRI _ = []
<a name="line-125"></a>
<a name="line-126"></a>
<a name="line-127"></a>patchRegs :: Instr -> (Reg -> Reg) -> Instr
<a name="line-128"></a>patchRegs instr env = case instr of
<a name="line-129"></a> SPILL reg slot -> SPILL (env reg) slot
<a name="line-130"></a> RELOAD slot reg -> RELOAD slot (env reg)
<a name="line-131"></a> LD sz reg addr -> LD sz (env reg) (fixAddr addr)
<a name="line-132"></a> LDA reg addr -> LDA (env reg) (fixAddr addr)
<a name="line-133"></a> LDAH reg addr -> LDAH (env reg) (fixAddr addr)
<a name="line-134"></a> LDGP reg addr -> LDGP (env reg) (fixAddr addr)
<a name="line-135"></a> LDI sz reg imm -> LDI sz (env reg) imm
<a name="line-136"></a> ST sz reg addr -> ST sz (env reg) (fixAddr addr)
<a name="line-137"></a> CLR reg -> CLR (env reg)
<a name="line-138"></a> ABS sz ar reg -> ABS sz (fixRI ar) (env reg)
<a name="line-139"></a> NEG sz ov ar reg -> NEG sz ov (fixRI ar) (env reg)
<a name="line-140"></a> ADD sz ov r1 ar r2 -> ADD sz ov (env r1) (fixRI ar) (env r2)
<a name="line-141"></a> SADD sz sc r1 ar r2 -> SADD sz sc (env r1) (fixRI ar) (env r2)
<a name="line-142"></a> SUB sz ov r1 ar r2 -> SUB sz ov (env r1) (fixRI ar) (env r2)
<a name="line-143"></a> SSUB sz sc r1 ar r2 -> SSUB sz sc (env r1) (fixRI ar) (env r2)
<a name="line-144"></a> MUL sz ov r1 ar r2 -> MUL sz ov (env r1) (fixRI ar) (env r2)
<a name="line-145"></a> DIV sz un r1 ar r2 -> DIV sz un (env r1) (fixRI ar) (env r2)
<a name="line-146"></a> REM sz un r1 ar r2 -> REM sz un (env r1) (fixRI ar) (env r2)
<a name="line-147"></a> NOT ar reg -> NOT (fixRI ar) (env reg)
<a name="line-148"></a> AND r1 ar r2 -> AND (env r1) (fixRI ar) (env r2)
<a name="line-149"></a> ANDNOT r1 ar r2 -> ANDNOT (env r1) (fixRI ar) (env r2)
<a name="line-150"></a> OR r1 ar r2 -> OR (env r1) (fixRI ar) (env r2)
<a name="line-151"></a> ORNOT r1 ar r2 -> ORNOT (env r1) (fixRI ar) (env r2)
<a name="line-152"></a> XOR r1 ar r2 -> XOR (env r1) (fixRI ar) (env r2)
<a name="line-153"></a> XORNOT r1 ar r2 -> XORNOT (env r1) (fixRI ar) (env r2)
<a name="line-154"></a> SLL r1 ar r2 -> SLL (env r1) (fixRI ar) (env r2)
<a name="line-155"></a> SRL r1 ar r2 -> SRL (env r1) (fixRI ar) (env r2)
<a name="line-156"></a> SRA r1 ar r2 -> SRA (env r1) (fixRI ar) (env r2)
<a name="line-157"></a> ZAP r1 ar r2 -> ZAP (env r1) (fixRI ar) (env r2)
<a name="line-158"></a> ZAPNOT r1 ar r2 -> ZAPNOT (env r1) (fixRI ar) (env r2)
<a name="line-159"></a> CMP co r1 ar r2 -> CMP co (env r1) (fixRI ar) (env r2)
<a name="line-160"></a> FCLR reg -> FCLR (env reg)
<a name="line-161"></a> FABS r1 r2 -> FABS (env r1) (env r2)
<a name="line-162"></a> FNEG s r1 r2 -> FNEG s (env r1) (env r2)
<a name="line-163"></a> FADD s r1 r2 r3 -> FADD s (env r1) (env r2) (env r3)
<a name="line-164"></a> FDIV s r1 r2 r3 -> FDIV s (env r1) (env r2) (env r3)
<a name="line-165"></a> FMUL s r1 r2 r3 -> FMUL s (env r1) (env r2) (env r3)
<a name="line-166"></a> FSUB s r1 r2 r3 -> FSUB s (env r1) (env r2) (env r3)
<a name="line-167"></a> CVTxy s1 s2 r1 r2 -> CVTxy s1 s2 (env r1) (env r2)
<a name="line-168"></a> FCMP s co r1 r2 r3 -> FCMP s co (env r1) (env r2) (env r3)
<a name="line-169"></a> FMOV r1 r2 -> FMOV (env r1) (env r2)
<a name="line-170"></a> BI cond reg lbl -> BI cond (env reg) lbl
<a name="line-171"></a> BF cond reg lbl -> BF cond (env reg) lbl
<a name="line-172"></a> JMP reg addr hint -> JMP (env reg) (fixAddr addr) hint
<a name="line-173"></a> JSR reg addr i -> JSR (env reg) (fixAddr addr) i
<a name="line-174"></a> _ -> instr
<a name="line-175"></a> where
<a name="line-176"></a> fixAddr (AddrReg r1) = AddrReg (env r1)
<a name="line-177"></a> fixAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
<a name="line-178"></a> fixAddr other = other
<a name="line-179"></a>
<a name="line-180"></a> fixRI (RIReg r) = RIReg (env r)
<a name="line-181"></a> fixRI other = other
<a name="line-182"></a>
<a name="line-183"></a>
<a name="line-184"></a>mkSpillInstr
<a name="line-185"></a> :: Reg -- register to spill
<a name="line-186"></a> -> Int -- current stack delta
<a name="line-187"></a> -> Int -- spill slot to use
<a name="line-188"></a> -> Instr
<a name="line-189"></a>
<a name="line-190"></a>mkSpillInstr reg delta slot
<a name="line-191"></a> = let off = spillSlotToOffset slot
<a name="line-192"></a> in
<a name="line-193"></a> -- Alpha: spill below the stack pointer (?)
<a name="line-194"></a> ST sz dyn (spRel (- (off `div` 8)))
<a name="line-195"></a>
<a name="line-196"></a>
<a name="line-197"></a>mkLoadInstr
<a name="line-198"></a> :: Reg -- register to load
<a name="line-199"></a> -> Int -- current stack delta
<a name="line-200"></a> -> Int -- spill slot to use
<a name="line-201"></a> -> Instr
<a name="line-202"></a>mkLoadInstr reg delta slot
<a name="line-203"></a> = let off = spillSlotToOffset slot
<a name="line-204"></a> in
<a name="line-205"></a> LD sz dyn (spRel (- (off `div` 8)))
<a name="line-206"></a>
<a name="line-207"></a>
<a name="line-208"></a>mkBranchInstr
<a name="line-209"></a> :: BlockId
<a name="line-210"></a> -> [Instr]
<a name="line-211"></a>
<a name="line-212"></a>mkBranchInstr id = [BR id]
<a name="line-213"></a>
<a name="line-214"></a>-}</span>
<a name="line-215"></a>
<a name="line-216"></a>
<a name="line-217"></a>
<a name="line-218"></a>
</pre></body>
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