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ghc-ghc-devel-6.12.3-5.fc14.i686.rpm

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>ghc-6.12.3: The GHC API</TD
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>Source code</A
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><TD CLASS="section1"
>Synopsis</TD
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></TD
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><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ARegUsage"
>RegUsage</A
>  = <A HREF="#v%3ARU"
>RU</A
> [<A HREF="Reg.html#t%3AReg"
>Reg</A
>] [<A HREF="Reg.html#t%3AReg"
>Reg</A
>]</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AnoUsage"
>noUsage</A
> :: <A HREF="Instruction.html#t%3ARegUsage"
>RegUsage</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>type</SPAN
> <A HREF="#t%3ANatCmm"
>NatCmm</A
> instr = <A HREF="Cmm.html#t%3AGenCmm"
>GenCmm</A
> <A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
> [<A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
>] (<A HREF="Cmm.html#t%3AListGraph"
>ListGraph</A
> instr)</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>type</SPAN
> <A HREF="#t%3ANatCmmTop"
>NatCmmTop</A
> instr = <A HREF="Cmm.html#t%3AGenCmmTop"
>GenCmmTop</A
> <A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
> [<A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
>] (<A HREF="Cmm.html#t%3AListGraph"
>ListGraph</A
> instr)</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>type</SPAN
> <A HREF="#t%3ANatBasicBlock"
>NatBasicBlock</A
> instr = <A HREF="Cmm.html#t%3AGenBasicBlock"
>GenBasicBlock</A
> instr</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>class</SPAN
>  <A HREF="#t%3AInstruction"
>Instruction</A
> instr  <SPAN CLASS="keyword"
>where</SPAN
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="#v%3AregUsageOfInstr"
>regUsageOfInstr</A
> :: instr -&gt; <A HREF="Instruction.html#t%3ARegUsage"
>RegUsage</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3ApatchRegsOfInstr"
>patchRegsOfInstr</A
> :: instr -&gt; (<A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
>) -&gt; instr</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AisJumpishInstr"
>isJumpishInstr</A
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Bool.html#t%3ABool"
>Bool</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AjumpDestsOfInstr"
>jumpDestsOfInstr</A
> :: instr -&gt; [<A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
>]</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3ApatchJumpInstr"
>patchJumpInstr</A
> :: instr -&gt; (<A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
> -&gt; <A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
>) -&gt; instr</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AmkSpillInstr"
>mkSpillInstr</A
> :: <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; instr</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AmkLoadInstr"
>mkLoadInstr</A
> :: <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; instr</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AtakeDeltaInstr"
>takeDeltaInstr</A
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AisMetaInstr"
>isMetaInstr</A
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Bool.html#t%3ABool"
>Bool</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AmkRegRegMoveInstr"
>mkRegRegMoveInstr</A
> :: <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; instr</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AtakeRegRegMoveInstr"
>takeRegRegMoveInstr</A
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> (<A HREF="Reg.html#t%3AReg"
>Reg</A
>, <A HREF="Reg.html#t%3AReg"
>Reg</A
>)</TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AmkJumpInstr"
>mkJumpInstr</A
> :: <A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
> -&gt; [instr]</TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Documentation</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:RegUsage"
><A NAME="t%3ARegUsage"
></A
></A
><B
>RegUsage</B
>  </TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#RegUsage"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
><P
>Holds a list of source and destination registers used by a
	particular instruction. 
</P
><P
>Machine registers that are pre-allocated to stgRegs are filtered
	out, because they are uninteresting from a register allocation
	standpoint.  (We wouldn't want them to end up on the free list!) 
</P
><P
>As far as we are concerned, the fixed registers simply don't exist
	(for allocation purposes, anyway).
</P
></TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:RU"
><A NAME="v%3ARU"
></A
></A
><B
>RU</B
> [<A HREF="Reg.html#t%3AReg"
>Reg</A
>] [<A HREF="Reg.html#t%3AReg"
>Reg</A
>]</TD
><TD CLASS="rdoc"
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:noUsage"
><A NAME="v%3AnoUsage"
></A
></A
><B
>noUsage</B
> :: <A HREF="Instruction.html#t%3ARegUsage"
>RegUsage</A
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#noUsage"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>No regs read or written to.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>type</SPAN
> <A NAME="t:NatCmm"
><A NAME="t%3ANatCmm"
></A
></A
><B
>NatCmm</B
> instr = <A HREF="Cmm.html#t%3AGenCmm"
>GenCmm</A
> <A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
> [<A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
>] (<A HREF="Cmm.html#t%3AListGraph"
>ListGraph</A
> instr)</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#NatCmm"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>type</SPAN
> <A NAME="t:NatCmmTop"
><A NAME="t%3ANatCmmTop"
></A
></A
><B
>NatCmmTop</B
> instr = <A HREF="Cmm.html#t%3AGenCmmTop"
>GenCmmTop</A
> <A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
> [<A HREF="Cmm.html#t%3ACmmStatic"
>CmmStatic</A
>] (<A HREF="Cmm.html#t%3AListGraph"
>ListGraph</A
> instr)</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#NatCmmTop"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>type</SPAN
> <A NAME="t:NatBasicBlock"
><A NAME="t%3ANatBasicBlock"
></A
></A
><B
>NatBasicBlock</B
> instr = <A HREF="Cmm.html#t%3AGenBasicBlock"
>GenBasicBlock</A
> instr</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#NatBasicBlock"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>class</SPAN
>  <A NAME="t:Instruction"
><A NAME="t%3AInstruction"
></A
></A
><B
>Instruction</B
> instr  <SPAN CLASS="keyword"
>where</SPAN
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#Instruction"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Common things that we can do with instructions, on all architectures.
	These are used by the shared parts of the native code generator,
	specifically the register allocators.
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="section4"
>Methods</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:regUsageOfInstr"
><A NAME="v%3AregUsageOfInstr"
></A
></A
><B
>regUsageOfInstr</B
> :: instr -&gt; <A HREF="Instruction.html#t%3ARegUsage"
>RegUsage</A
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#regUsageOfInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Get the registers that are being used by this instruction.
	regUsage doesn't need to do any trickery for jumps and such.  
	Just state precisely the regs read and written by that insn.  
	The consequences of control flow transfers, as far as register
 	allocation goes, are taken care of by the register allocator.
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:patchRegsOfInstr"
><A NAME="v%3ApatchRegsOfInstr"
></A
></A
><B
>patchRegsOfInstr</B
> :: instr -&gt; (<A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
>) -&gt; instr</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#patchRegsOfInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Apply a given mapping to all the register references in this
	instruction.
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:isJumpishInstr"
><A NAME="v%3AisJumpishInstr"
></A
></A
><B
>isJumpishInstr</B
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Bool.html#t%3ABool"
>Bool</A
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#isJumpishInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Checks whether this instruction is a jump/branch instruction. 
	One that can change the flow of control in a way that the 
	register allocator needs to worry about. 
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:jumpDestsOfInstr"
><A NAME="v%3AjumpDestsOfInstr"
></A
></A
><B
>jumpDestsOfInstr</B
> :: instr -&gt; [<A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
>]</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#jumpDestsOfInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Give the possible destinations of this jump instruction.
	Must be defined for all jumpish instructions.
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:patchJumpInstr"
><A NAME="v%3ApatchJumpInstr"
></A
></A
><B
>patchJumpInstr</B
> :: instr -&gt; (<A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
> -&gt; <A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
>) -&gt; instr</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#patchJumpInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Change the destination of this jump instruction.
	Used in the linear allocator when adding fixup blocks for join
	points.
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:mkSpillInstr"
><A NAME="v%3AmkSpillInstr"
></A
></A
><B
>mkSpillInstr</B
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#mkSpillInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="arg"
>:: <A HREF="Reg.html#t%3AReg"
>Reg</A
></TD
><TD CLASS="rdoc"
>the reg to spill
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>the current stack delta
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>spill slot to use
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; instr</TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="ndoc" COLSPAN="2"
>An instruction to spill a register into a spill slot.
</TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:mkLoadInstr"
><A NAME="v%3AmkLoadInstr"
></A
></A
><B
>mkLoadInstr</B
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#mkLoadInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="arg"
>:: <A HREF="Reg.html#t%3AReg"
>Reg</A
></TD
><TD CLASS="rdoc"
>the reg to reload.
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>the current stack delta
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>the spill slot to use
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; instr</TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="ndoc" COLSPAN="2"
>An instruction to reload a register from a spill slot.
</TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:takeDeltaInstr"
><A NAME="v%3AtakeDeltaInstr"
></A
></A
><B
>takeDeltaInstr</B
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#takeDeltaInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>See if this instruction is telling us the current C stack delta
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:isMetaInstr"
><A NAME="v%3AisMetaInstr"
></A
></A
><B
>isMetaInstr</B
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Bool.html#t%3ABool"
>Bool</A
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#isMetaInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
><P
>Check whether this instruction is some meta thing inserted into 
	the instruction stream for other purposes.
</P
><P
>Not something that has to be treated as a real machine instruction
	and have its registers allocated.
</P
><P
>eg, comments, delta, ldata, etc. 
</P
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:mkRegRegMoveInstr"
><A NAME="v%3AmkRegRegMoveInstr"
></A
></A
><B
>mkRegRegMoveInstr</B
></TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#mkRegRegMoveInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="arg"
>:: <A HREF="Reg.html#t%3AReg"
>Reg</A
></TD
><TD CLASS="rdoc"
>source register
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
></TD
><TD CLASS="rdoc"
>destination register
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; instr</TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="ndoc" COLSPAN="2"
>Copy the value in a register to another one.
	Must work for all register classes.
</TD
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></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:takeRegRegMoveInstr"
><A NAME="v%3AtakeRegRegMoveInstr"
></A
></A
><B
>takeRegRegMoveInstr</B
> :: instr -&gt; <A HREF="../base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> (<A HREF="Reg.html#t%3AReg"
>Reg</A
>, <A HREF="Reg.html#t%3AReg"
>Reg</A
>)</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#takeRegRegMoveInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Take the source and destination from this reg -&gt; reg move instruction
	or Nothing if it's not one
</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:mkJumpInstr"
><A NAME="v%3AmkJumpInstr"
></A
></A
><B
>mkJumpInstr</B
> :: <A HREF="BlockId.html#t%3ABlockId"
>BlockId</A
> -&gt; [instr]</TD
><TD CLASS="declbut"
><A HREF="src/Instruction.html#mkJumpInstr"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Make an unconditional jump instruction.
	For architectures with branch delay slots, its ok to put
	a NOP after the jump. Don't fill the delay slot with an
	instruction that references regs or you'll confuse the 
	linear allocator.
</TD
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> Instances</TD
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><TD CLASS="decl"
><A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> <A HREF="X86-Instr.html#t%3AInstr"
>Instr</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> <A HREF="PPC-Instr.html#t%3AInstr"
>Instr</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> <A HREF="SPARC-Instr.html#t%3AInstr"
>Instr</A
></TD
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