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<TITLE>3.10.3 Semaphore locking (mcs51/ds390)</TITLE>
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<H2><A NAME="SECTION004103000000000000000"></A><A NAME="1804"></A>
<BR>
3.10.3 Semaphore locking (mcs51/ds390)
</H2>

<P>
Some architectures (mcs51/ds390) have an atomic<A NAME="1805"></A> bit
test and clear instruction. These type of instructions are typically
used in preemptive multitasking systems, where a routine f.e. claims
the use of a data structure ('acquires a lock<A NAME="1806"></A> on it'),
makes some modifications and then releases the lock when the data
structure is consistent again. The instruction may also be used if
interrupt and non-interrupt code have to compete for a resource. With
the atomic bit test and clear instruction interrupts<A NAME="1807"></A>
don't have to be disabled for the locking operation. 

<P>
SDCC generates this instruction if the source follows this pattern:
<BLOCKQUOTE>
<TT>volatile<A NAME="1809"></A> bit resource_is_free; </TT>&nbsp;
<BR>&nbsp;
<BR><TT>if (resource_is_free) </TT>&nbsp;
<BR><TT>&nbsp;&nbsp;{ </TT>&nbsp;
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;resource_is_free=0; </TT>&nbsp;
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;... </TT>&nbsp;
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;resource_is_free=1;</TT>&nbsp;
<BR><TT>&nbsp;&nbsp;} </TT>

</BLOCKQUOTE>
Note, mcs51 and ds390 support only an atomic<A NAME="1818"></A> bit test
and <I>clear</I> instruction (as opposed to atomic bit test and <I>set).</I>

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2011-03-20
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