<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.14"/>
<meta name="viewport" content="width=device-width, initial-scale=1"/>
<title>Crypto++: cpu.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
<tbody>
<tr style="height: 56px;">
<td id="projectalign" style="padding-left: 0.5em;">
<div id="projectname">Crypto++
 <span id="projectnumber">7.0</span>
</div>
<div id="projectbrief">Free C++ class library of cryptographic schemes</div>
</td>
</tr>
</tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.14 -->
<script type="text/javascript" src="menudata.js"></script>
<script type="text/javascript" src="menu.js"></script>
<script type="text/javascript">
/* @license magnet:?xt=urn:btih:cf05388f2679ee054f2beb29a391d25f4e673ac3&dn=gpl-2.0.txt GPL-v2 */
$(function() {
initMenu('',false,false,'search.php','Search');
});
/* @license-end */</script>
<div id="main-nav"></div>
</div><!-- top -->
<div class="header">
<div class="summary">
<a href="#define-members">Macros</a> </div>
<div class="headertitle">
<div class="title">cpu.h File Reference</div> </div>
</div><!--header-->
<div class="contents">
<p>Functions for CPU features and intrinsics.
<a href="#details">More...</a></p>
<p><a href="cpu_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a7b99dc1e1c86b4897498c2d436ead1b5"><td class="memItemLeft" align="right" valign="top"><a id="a7b99dc1e1c86b4897498c2d436ead1b5"></a>
#define </td><td class="memItemRight" valign="bottom"><b>NEW_LINE</b></td></tr>
<tr class="separator:a7b99dc1e1c86b4897498c2d436ead1b5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a959658203a1521f68c9677cee97dd29b"><td class="memItemLeft" align="right" valign="top"><a id="a959658203a1521f68c9677cee97dd29b"></a>
#define </td><td class="memItemRight" valign="bottom"><b>INTEL_PREFIX</b></td></tr>
<tr class="separator:a959658203a1521f68c9677cee97dd29b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4e5041e8c25497a00e6f0951e5423826"><td class="memItemLeft" align="right" valign="top"><a id="a4e5041e8c25497a00e6f0951e5423826"></a>
#define </td><td class="memItemRight" valign="bottom"><b>INTEL_NOPREFIX</b></td></tr>
<tr class="separator:a4e5041e8c25497a00e6f0951e5423826"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a85c565d81572bce3fd3d0d54c39a1e59"><td class="memItemLeft" align="right" valign="top"><a id="a85c565d81572bce3fd3d0d54c39a1e59"></a>
#define </td><td class="memItemRight" valign="bottom"><b>ATT_PREFIX</b></td></tr>
<tr class="separator:a85c565d81572bce3fd3d0d54c39a1e59"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a26f50315a7e5244e60133fe0ce28e179"><td class="memItemLeft" align="right" valign="top"><a id="a26f50315a7e5244e60133fe0ce28e179"></a>
#define </td><td class="memItemRight" valign="bottom"><b>ATT_NOPREFIX</b></td></tr>
<tr class="separator:a26f50315a7e5244e60133fe0ce28e179"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a567cb6ffbc2864016463783b5cf92d3c"><td class="memItemLeft" align="right" valign="top"><a id="a567cb6ffbc2864016463783b5cf92d3c"></a>
#define </td><td class="memItemRight" valign="bottom"><b>CRYPTOPP_CPUID_AVAILABLE</b>   1</td></tr>
<tr class="separator:a567cb6ffbc2864016463783b5cf92d3c"><td class="memSeparator" colspan="2"> </td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">IA-32 CPU FEATURES</div></td></tr>
<tr class="memitem:a962fa16f6d3a8a518912b39c3ea84062"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a962fa16f6d3a8a518912b39c3ea84062">HasSSE2</a> ()</td></tr>
<tr class="memdesc:a962fa16f6d3a8a518912b39c3ea84062"><td class="mdescLeft"> </td><td class="mdescRight">Determines SSE2 availability. <a href="#a962fa16f6d3a8a518912b39c3ea84062">More...</a><br /></td></tr>
<tr class="separator:a962fa16f6d3a8a518912b39c3ea84062"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3a513219c66d57b18cc0a6e0ff28f20c"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a3a513219c66d57b18cc0a6e0ff28f20c">HasSSSE3</a> ()</td></tr>
<tr class="memdesc:a3a513219c66d57b18cc0a6e0ff28f20c"><td class="mdescLeft"> </td><td class="mdescRight">Determines SSSE3 availability. <a href="#a3a513219c66d57b18cc0a6e0ff28f20c">More...</a><br /></td></tr>
<tr class="separator:a3a513219c66d57b18cc0a6e0ff28f20c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afeba098225030e7a23454cc7abbdec7a"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#afeba098225030e7a23454cc7abbdec7a">HasSSE41</a> ()</td></tr>
<tr class="memdesc:afeba098225030e7a23454cc7abbdec7a"><td class="mdescLeft"> </td><td class="mdescRight">Determines SSE4.1 availability. <a href="#afeba098225030e7a23454cc7abbdec7a">More...</a><br /></td></tr>
<tr class="separator:afeba098225030e7a23454cc7abbdec7a"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0dc923aa941e17016d06b1f133f65f18"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a0dc923aa941e17016d06b1f133f65f18">HasSSE42</a> ()</td></tr>
<tr class="memdesc:a0dc923aa941e17016d06b1f133f65f18"><td class="mdescLeft"> </td><td class="mdescRight">Determines SSE4.2 availability. <a href="#a0dc923aa941e17016d06b1f133f65f18">More...</a><br /></td></tr>
<tr class="separator:a0dc923aa941e17016d06b1f133f65f18"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a798d0d1732f761b34e4b127335a111c1"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a798d0d1732f761b34e4b127335a111c1">HasAESNI</a> ()</td></tr>
<tr class="memdesc:a798d0d1732f761b34e4b127335a111c1"><td class="mdescLeft"> </td><td class="mdescRight">Determines AES-NI availability. <a href="#a798d0d1732f761b34e4b127335a111c1">More...</a><br /></td></tr>
<tr class="separator:a798d0d1732f761b34e4b127335a111c1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a07cfbea5dcfb03d7ede705f71b8e46d7"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a07cfbea5dcfb03d7ede705f71b8e46d7">HasCLMUL</a> ()</td></tr>
<tr class="memdesc:a07cfbea5dcfb03d7ede705f71b8e46d7"><td class="mdescLeft"> </td><td class="mdescRight">Determines Carryless Multiply availability. <a href="#a07cfbea5dcfb03d7ede705f71b8e46d7">More...</a><br /></td></tr>
<tr class="separator:a07cfbea5dcfb03d7ede705f71b8e46d7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a855707a423287740d7301faa4a628797"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a855707a423287740d7301faa4a628797">HasSHA</a> ()</td></tr>
<tr class="memdesc:a855707a423287740d7301faa4a628797"><td class="mdescLeft"> </td><td class="mdescRight">Determines SHA availability. <a href="#a855707a423287740d7301faa4a628797">More...</a><br /></td></tr>
<tr class="separator:a855707a423287740d7301faa4a628797"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a85ee28b754e00aa931fddd1b7dd306d4"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a85ee28b754e00aa931fddd1b7dd306d4">HasADX</a> ()</td></tr>
<tr class="memdesc:a85ee28b754e00aa931fddd1b7dd306d4"><td class="mdescLeft"> </td><td class="mdescRight">Determines ADX availability. <a href="#a85ee28b754e00aa931fddd1b7dd306d4">More...</a><br /></td></tr>
<tr class="separator:a85ee28b754e00aa931fddd1b7dd306d4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:accc516c1ea183a7679f7ff8db65b50d7"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#accc516c1ea183a7679f7ff8db65b50d7">IsP4</a> ()</td></tr>
<tr class="memdesc:accc516c1ea183a7679f7ff8db65b50d7"><td class="mdescLeft"> </td><td class="mdescRight">Determines if the CPU is an Intel P4. <a href="#accc516c1ea183a7679f7ff8db65b50d7">More...</a><br /></td></tr>
<tr class="separator:accc516c1ea183a7679f7ff8db65b50d7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5076f994ec8575113a191accc4a8376e"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a5076f994ec8575113a191accc4a8376e">HasRDRAND</a> ()</td></tr>
<tr class="memdesc:a5076f994ec8575113a191accc4a8376e"><td class="mdescLeft"> </td><td class="mdescRight">Determines <a class="el" href="class_r_d_r_a_n_d.html" title="Hardware generated random numbers using RDRAND instruction. ">RDRAND</a> availability. <a href="#a5076f994ec8575113a191accc4a8376e">More...</a><br /></td></tr>
<tr class="separator:a5076f994ec8575113a191accc4a8376e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af7125da1236a58ece8e109350009711e"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#af7125da1236a58ece8e109350009711e">HasRDSEED</a> ()</td></tr>
<tr class="memdesc:af7125da1236a58ece8e109350009711e"><td class="mdescLeft"> </td><td class="mdescRight">Determines <a class="el" href="class_r_d_s_e_e_d.html" title="Hardware generated random numbers using RDSEED instruction. ">RDSEED</a> availability. <a href="#af7125da1236a58ece8e109350009711e">More...</a><br /></td></tr>
<tr class="separator:af7125da1236a58ece8e109350009711e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a05706e0c94ae8651b12f3f5de1289763"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a05706e0c94ae8651b12f3f5de1289763">HasPadlockRNG</a> ()</td></tr>
<tr class="memdesc:a05706e0c94ae8651b12f3f5de1289763"><td class="mdescLeft"> </td><td class="mdescRight">Determines Padlock RNG availability. <a href="#a05706e0c94ae8651b12f3f5de1289763">More...</a><br /></td></tr>
<tr class="separator:a05706e0c94ae8651b12f3f5de1289763"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0b8955dc607e2ba44edb5594a9bef719"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a0b8955dc607e2ba44edb5594a9bef719">HasPadlockACE</a> ()</td></tr>
<tr class="memdesc:a0b8955dc607e2ba44edb5594a9bef719"><td class="mdescLeft"> </td><td class="mdescRight">Determines Padlock ACE availability. <a href="#a0b8955dc607e2ba44edb5594a9bef719">More...</a><br /></td></tr>
<tr class="separator:a0b8955dc607e2ba44edb5594a9bef719"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a91222d7f948868a72a0f85668e02c98e"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a91222d7f948868a72a0f85668e02c98e">HasPadlockACE2</a> ()</td></tr>
<tr class="memdesc:a91222d7f948868a72a0f85668e02c98e"><td class="mdescLeft"> </td><td class="mdescRight">Determines Padlock ACE2 availability. <a href="#a91222d7f948868a72a0f85668e02c98e">More...</a><br /></td></tr>
<tr class="separator:a91222d7f948868a72a0f85668e02c98e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0f3efaa348070d2d87e8944b0d4767ce"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a0f3efaa348070d2d87e8944b0d4767ce">HasPadlockPHE</a> ()</td></tr>
<tr class="memdesc:a0f3efaa348070d2d87e8944b0d4767ce"><td class="mdescLeft"> </td><td class="mdescRight">Determines Padlock PHE availability. <a href="#a0f3efaa348070d2d87e8944b0d4767ce">More...</a><br /></td></tr>
<tr class="separator:a0f3efaa348070d2d87e8944b0d4767ce"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aef8af93f0f3563fa88e7d6ad3902bbc3"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#aef8af93f0f3563fa88e7d6ad3902bbc3">HasPadlockPMM</a> ()</td></tr>
<tr class="memdesc:aef8af93f0f3563fa88e7d6ad3902bbc3"><td class="mdescLeft"> </td><td class="mdescRight">Determines Padlock PMM availability. <a href="#aef8af93f0f3563fa88e7d6ad3902bbc3">More...</a><br /></td></tr>
<tr class="separator:aef8af93f0f3563fa88e7d6ad3902bbc3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7c008779986afa9c0463b2bc8fe17042"><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a7c008779986afa9c0463b2bc8fe17042">GetCacheLineSize</a> ()</td></tr>
<tr class="memdesc:a7c008779986afa9c0463b2bc8fe17042"><td class="mdescLeft"> </td><td class="mdescRight">Provides the cache line size. <a href="#a7c008779986afa9c0463b2bc8fe17042">More...</a><br /></td></tr>
<tr class="separator:a7c008779986afa9c0463b2bc8fe17042"><td class="memSeparator" colspan="2"> </td></tr>
<tr><td colspan="2"><div class="groupHeader">ARM A-32, Aarch32 and AArch64 CPU FEATURES</div></td></tr>
<tr class="memitem:a1bc02803e38ce67dd68d23600f59f71f"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a1bc02803e38ce67dd68d23600f59f71f">HasNEON</a> ()</td></tr>
<tr class="memdesc:a1bc02803e38ce67dd68d23600f59f71f"><td class="mdescLeft"> </td><td class="mdescRight">Determine if an ARM processor has Advanced SIMD available. <a href="#a1bc02803e38ce67dd68d23600f59f71f">More...</a><br /></td></tr>
<tr class="separator:a1bc02803e38ce67dd68d23600f59f71f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaa6a27c8ca66a700ccba214c4b69bcd4"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#aaa6a27c8ca66a700ccba214c4b69bcd4">HasPMULL</a> ()</td></tr>
<tr class="memdesc:aaa6a27c8ca66a700ccba214c4b69bcd4"><td class="mdescLeft"> </td><td class="mdescRight">Determine if an ARM processor provides Polynomial Multiplication. <a href="#aaa6a27c8ca66a700ccba214c4b69bcd4">More...</a><br /></td></tr>
<tr class="separator:aaa6a27c8ca66a700ccba214c4b69bcd4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a84c5040b823753bcd1f5413af059f22c"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a84c5040b823753bcd1f5413af059f22c">HasCRC32</a> ()</td></tr>
<tr class="memdesc:a84c5040b823753bcd1f5413af059f22c"><td class="mdescLeft"> </td><td class="mdescRight">Determine if an ARM processor has <a class="el" href="class_c_r_c32.html" title="CRC-32 Checksum Calculation. ">CRC32</a> available. <a href="#a84c5040b823753bcd1f5413af059f22c">More...</a><br /></td></tr>
<tr class="separator:a84c5040b823753bcd1f5413af059f22c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a01958720925de0cb8515345758825326"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a01958720925de0cb8515345758825326">HasAES</a> ()</td></tr>
<tr class="memdesc:a01958720925de0cb8515345758825326"><td class="mdescLeft"> </td><td class="mdescRight">Determine if an ARM processor has <a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> available. <a href="#a01958720925de0cb8515345758825326">More...</a><br /></td></tr>
<tr class="separator:a01958720925de0cb8515345758825326"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a8ef26827072113945e44a7895f63ff35"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a8ef26827072113945e44a7895f63ff35">HasSHA1</a> ()</td></tr>
<tr class="memdesc:a8ef26827072113945e44a7895f63ff35"><td class="mdescLeft"> </td><td class="mdescRight">Determine if an ARM processor has <a class="el" href="class_s_h_a1.html" title="SHA-1 message digest. ">SHA1</a> available. <a href="#a8ef26827072113945e44a7895f63ff35">More...</a><br /></td></tr>
<tr class="separator:a8ef26827072113945e44a7895f63ff35"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a2564411b398029e7201a48469e30c9bf"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a2564411b398029e7201a48469e30c9bf">HasSHA2</a> ()</td></tr>
<tr class="memdesc:a2564411b398029e7201a48469e30c9bf"><td class="mdescLeft"> </td><td class="mdescRight">Determine if an ARM processor has SHA2 available. <a href="#a2564411b398029e7201a48469e30c9bf">More...</a><br /></td></tr>
<tr class="separator:a2564411b398029e7201a48469e30c9bf"><td class="memSeparator" colspan="2"> </td></tr>
<tr><td colspan="2"><div class="groupHeader">POWERPC CPU FEATURES</div></td></tr>
<tr class="memitem:a0e0902fb52a61c2c0845be848934f6b3"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a0e0902fb52a61c2c0845be848934f6b3">HasAltivec</a> ()</td></tr>
<tr class="memdesc:a0e0902fb52a61c2c0845be848934f6b3"><td class="mdescLeft"> </td><td class="mdescRight">Determine if a PowerPC processor has Altivec available. <a href="#a0e0902fb52a61c2c0845be848934f6b3">More...</a><br /></td></tr>
<tr class="separator:a0e0902fb52a61c2c0845be848934f6b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a899003e15d0efcea5e96c40d6ed683f0"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a899003e15d0efcea5e96c40d6ed683f0">HasPower7</a> ()</td></tr>
<tr class="memdesc:a899003e15d0efcea5e96c40d6ed683f0"><td class="mdescLeft"> </td><td class="mdescRight">Determine if a PowerPC processor has Power8 available. <a href="#a899003e15d0efcea5e96c40d6ed683f0">More...</a><br /></td></tr>
<tr class="separator:a899003e15d0efcea5e96c40d6ed683f0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4fb317243ae628c4bc9cd264200688ca"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a4fb317243ae628c4bc9cd264200688ca">HasPower8</a> ()</td></tr>
<tr class="memdesc:a4fb317243ae628c4bc9cd264200688ca"><td class="mdescLeft"> </td><td class="mdescRight">Determine if a PowerPC processor has Power8 available. <a href="#a4fb317243ae628c4bc9cd264200688ca">More...</a><br /></td></tr>
<tr class="separator:a4fb317243ae628c4bc9cd264200688ca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aaa3d1639456458a8681d2cddb06d72ee"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#aaa3d1639456458a8681d2cddb06d72ee">HasSHA256</a> ()</td></tr>
<tr class="memdesc:aaa3d1639456458a8681d2cddb06d72ee"><td class="mdescLeft"> </td><td class="mdescRight">Determine if a PowerPC processor has <a class="el" href="class_s_h_a256.html" title="SHA-256 message digest. ">SHA256</a> available. <a href="#aaa3d1639456458a8681d2cddb06d72ee">More...</a><br /></td></tr>
<tr class="separator:aaa3d1639456458a8681d2cddb06d72ee"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1d287c17e472e6d8e0116647786d49f3"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="cpu_8h.html#a1d287c17e472e6d8e0116647786d49f3">HasSHA512</a> ()</td></tr>
<tr class="memdesc:a1d287c17e472e6d8e0116647786d49f3"><td class="mdescLeft"> </td><td class="mdescRight">Determine if a PowerPC processor has <a class="el" href="class_s_h_a512.html" title="SHA-512 message digest. ">SHA512</a> available. <a href="#a1d287c17e472e6d8e0116647786d49f3">More...</a><br /></td></tr>
<tr class="separator:a1d287c17e472e6d8e0116647786d49f3"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Functions for CPU features and intrinsics. </p>
<p>The CPU functions are used in IA-32, ARM and PowerPC code paths. The functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.</p>
<p>Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms a two-part strategy is used. First, the library attempts to *Query* the OS for a feature, like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe* the cpu executing an instruction and an observe a SIGILL if unsupported. The general pattern used by the library is: </p><pre>
g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();
g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();
g_hasAES = CPU_QueryAES() || CPU_ProbeAES();
</pre><p>Generally speaking, CPU_Query() is in the source file <code><a class="el" href="cpu_8cpp_source.html">cpu.cpp</a></code> because it does not require special architectural flags. CPU_Probe() is in a source file that recieves architectural flags, like <code><a class="el" href="sse-simd_8cpp_source.html">sse-simd.cpp</a></code>, <code><a class="el" href="neon-simd_8cpp_source.html">neon-simd.cpp</a></code> and <code><a class="el" href="ppc-simd_8cpp_source.html">ppc-simd.cpp</a></code>. For example, compiling <code><a class="el" href="neon-simd_8cpp_source.html">neon-simd.cpp</a></code> on an ARM64 machine will have <code>-march=armv8-a</code> applied during a compile to make the instruction set architecture (ISA) available.</p>
<p>The cpu probes are expensive when compared to a standard OS feature query. The library also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL experienced the same problem and moved away from SIGILL probes on Apple. </p>
<p class="definition">Definition in file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div><h2 class="groupheader">Function Documentation</h2>
<a id="a962fa16f6d3a8a518912b39c3ea84062"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a962fa16f6d3a8a518912b39c3ea84062">◆ </a></span>HasSSE2()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSSE2 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines SSE2 availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if SSE2 is determined to be available, false otherwise</dd></dl>
<p>MMX, SSE and SSE2 are core processor features for x86_64, and the function always returns true for the platform. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00114">114</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a3a513219c66d57b18cc0a6e0ff28f20c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3a513219c66d57b18cc0a6e0ff28f20c">◆ </a></span>HasSSSE3()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSSSE3 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines SSSE3 availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if SSSE3 is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a3a513219c66d57b18cc0a6e0ff28f20c" title="Determines SSSE3 availability. ">HasSSSE3()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00129">129</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="afeba098225030e7a23454cc7abbdec7a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afeba098225030e7a23454cc7abbdec7a">◆ </a></span>HasSSE41()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSSE41 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines SSE4.1 availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if SSE4.1 is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#afeba098225030e7a23454cc7abbdec7a" title="Determines SSE4.1 availability. ">HasSSE41()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00140">140</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a0dc923aa941e17016d06b1f133f65f18"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0dc923aa941e17016d06b1f133f65f18">◆ </a></span>HasSSE42()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSSE42 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines SSE4.2 availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if SSE4.2 is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a0dc923aa941e17016d06b1f133f65f18" title="Determines SSE4.2 availability. ">HasSSE42()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00151">151</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a798d0d1732f761b34e4b127335a111c1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a798d0d1732f761b34e4b127335a111c1">◆ </a></span>HasAESNI()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasAESNI </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines AES-NI availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if AES-NI is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a798d0d1732f761b34e4b127335a111c1" title="Determines AES-NI availability. ">HasAESNI()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00162">162</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a07cfbea5dcfb03d7ede705f71b8e46d7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a07cfbea5dcfb03d7ede705f71b8e46d7">◆ </a></span>HasCLMUL()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasCLMUL </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines Carryless Multiply availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if pclmulqdq is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a07cfbea5dcfb03d7ede705f71b8e46d7" title="Determines Carryless Multiply availability. ">HasCLMUL()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00173">173</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a855707a423287740d7301faa4a628797"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a855707a423287740d7301faa4a628797">◆ </a></span>HasSHA()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSHA </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines SHA availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if SHA is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a855707a423287740d7301faa4a628797" title="Determines SHA availability. ">HasSHA()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00184">184</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a85ee28b754e00aa931fddd1b7dd306d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a85ee28b754e00aa931fddd1b7dd306d4">◆ </a></span>HasADX()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasADX </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines ADX availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if ADX is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a85ee28b754e00aa931fddd1b7dd306d4" title="Determines ADX availability. ">HasADX()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00195">195</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="accc516c1ea183a7679f7ff8db65b50d7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#accc516c1ea183a7679f7ff8db65b50d7">◆ </a></span>IsP4()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool IsP4 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines if the CPU is an Intel P4. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the CPU is a P4, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#accc516c1ea183a7679f7ff8db65b50d7" title="Determines if the CPU is an Intel P4. ">IsP4()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00206">206</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a5076f994ec8575113a191accc4a8376e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5076f994ec8575113a191accc4a8376e">◆ </a></span>HasRDRAND()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasRDRAND </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines <a class="el" href="class_r_d_r_a_n_d.html" title="Hardware generated random numbers using RDRAND instruction. ">RDRAND</a> availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if <a class="el" href="class_r_d_r_a_n_d.html" title="Hardware generated random numbers using RDRAND instruction. ">RDRAND</a> is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a5076f994ec8575113a191accc4a8376e" title="Determines RDRAND availability. ">HasRDRAND()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00217">217</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="af7125da1236a58ece8e109350009711e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af7125da1236a58ece8e109350009711e">◆ </a></span>HasRDSEED()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasRDSEED </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines <a class="el" href="class_r_d_s_e_e_d.html" title="Hardware generated random numbers using RDSEED instruction. ">RDSEED</a> availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if <a class="el" href="class_r_d_s_e_e_d.html" title="Hardware generated random numbers using RDSEED instruction. ">RDSEED</a> is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#af7125da1236a58ece8e109350009711e" title="Determines RDSEED availability. ">HasRDSEED()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00228">228</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a05706e0c94ae8651b12f3f5de1289763"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a05706e0c94ae8651b12f3f5de1289763">◆ </a></span>HasPadlockRNG()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPadlockRNG </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines Padlock RNG availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if VIA Padlock RNG is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a05706e0c94ae8651b12f3f5de1289763" title="Determines Padlock RNG availability. ">HasPadlockRNG()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00239">239</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a0b8955dc607e2ba44edb5594a9bef719"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0b8955dc607e2ba44edb5594a9bef719">◆ </a></span>HasPadlockACE()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPadlockACE </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines Padlock ACE availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if VIA Padlock ACE is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a0b8955dc607e2ba44edb5594a9bef719" title="Determines Padlock ACE availability. ">HasPadlockACE()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00250">250</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a91222d7f948868a72a0f85668e02c98e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a91222d7f948868a72a0f85668e02c98e">◆ </a></span>HasPadlockACE2()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPadlockACE2 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines Padlock ACE2 availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if VIA Padlock ACE2 is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a91222d7f948868a72a0f85668e02c98e" title="Determines Padlock ACE2 availability. ">HasPadlockACE2()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00261">261</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a0f3efaa348070d2d87e8944b0d4767ce"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0f3efaa348070d2d87e8944b0d4767ce">◆ </a></span>HasPadlockPHE()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPadlockPHE </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines Padlock PHE availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if VIA Padlock PHE is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#a0f3efaa348070d2d87e8944b0d4767ce" title="Determines Padlock PHE availability. ">HasPadlockPHE()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00272">272</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="aef8af93f0f3563fa88e7d6ad3902bbc3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aef8af93f0f3563fa88e7d6ad3902bbc3">◆ </a></span>HasPadlockPMM()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPadlockPMM </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determines Padlock PMM availability. </p>
<dl class="section return"><dt>Returns</dt><dd>true if VIA Padlock PMM is determined to be available, false otherwise</dd></dl>
<p><a class="el" href="cpu_8h.html#aef8af93f0f3563fa88e7d6ad3902bbc3" title="Determines Padlock PMM availability. ">HasPadlockPMM()</a> is a runtime check performed using CPUID </p><dl class="section note"><dt>Note</dt><dd>This function is only available on Intel IA-32 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00283">283</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a7c008779986afa9c0463b2bc8fe17042"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7c008779986afa9c0463b2bc8fe17042">◆ </a></span>GetCacheLineSize()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">int GetCacheLineSize </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Provides the cache line size. </p>
<dl class="section return"><dt>Returns</dt><dd>lower bound on the size of a cache line in bytes, if available</dd></dl>
<p><a class="el" href="cpu_8h.html#a7c008779986afa9c0463b2bc8fe17042" title="Provides the cache line size. ">GetCacheLineSize()</a> returns the lower bound on the size of a cache line, if it is available. If the value is not available at runtime, then 32 is returned for a 32-bit processor and 64 is returned for a 64-bit processor.</p>
<p>x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC and AIX also makes the value available to user space and it is also usually accurate. The ARM processor equivalent is a privileged instruction, so a compile time value is returned. </p>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00298">298</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a1bc02803e38ce67dd68d23600f59f71f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1bc02803e38ce67dd68d23600f59f71f">◆ </a></span>HasNEON()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasNEON </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if an ARM processor has Advanced SIMD available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of Advanced SIMD at runtime, false otherwise.</dd></dl>
<p>Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mfpu=neon</code> (32-bit) or <code>-march=armv8-a</code> (64-bit). Also see ARM's <code>__ARM_NEON</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on ARM-32, Aarch32 and Aarch64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00329">329</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="aaa6a27c8ca66a700ccba214c4b69bcd4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aaa6a27c8ca66a700ccba214c4b69bcd4">◆ </a></span>HasPMULL()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPMULL </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if an ARM processor provides Polynomial Multiplication. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of polynomial multiplications at runtime, false otherwise.</dd></dl>
<p>The multiplication instructions are available under Aarch32 and Aarch64.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-march=armv8-a+crypto</code>; while Apple requires <code>-arch arm64</code>. Also see ARM's <code>__ARM_FEATURE_CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on ARM-32, Aarch32 and Aarch64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00348">348</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a84c5040b823753bcd1f5413af059f22c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a84c5040b823753bcd1f5413af059f22c">◆ </a></span>HasCRC32()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasCRC32 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if an ARM processor has <a class="el" href="class_c_r_c32.html" title="CRC-32 Checksum Calculation. ">CRC32</a> available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of <a class="el" href="class_c_r_c32.html" title="CRC-32 Checksum Calculation. ">CRC32</a> at runtime, false otherwise.</dd></dl>
<p><a class="el" href="class_c_r_c32.html" title="CRC-32 Checksum Calculation. ">CRC32</a> instructions provide access to the processor's CRC-32 and CRC-32C instructions. They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and available under Aarch32 and Aarch64.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-march=armv8-a+crc</code>; while Apple requires <code>-arch arm64</code>. Also see ARM's <code>__ARM_FEATURE_CRC32</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on ARM-32, Aarch32 and Aarch64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00367">367</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a01958720925de0cb8515345758825326"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a01958720925de0cb8515345758825326">◆ </a></span>HasAES()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasAES </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if an ARM processor has <a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> available. </p>
<p>Determine if a PowerPC processor has <a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> available.</p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of <a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> at runtime, false otherwise.</dd></dl>
<p><a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> is part of the optional Crypto extensions on Aarch32 and Aarch64. They are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-march=armv8-a+crypto</code>; while Apple requires <code>-arch arm64</code>. Also see ARM's <code>__ARM_FEATURE_CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on ARM-32, Aarch32 and Aarch64 platforms</dd></dl>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of <a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> at runtime, false otherwise.</dd></dl>
<p><a class="el" href="class_a_e_s.html" title="AES block cipher (Rijndael) ">AES</a> is part of the in-crypto extensions on Power8 and Power9.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mcpu=power8</code>; while IBM XL C/C++ compilers require <code>-qarch=pwr8 -qaltivec</code>. Also see PowerPC's <code>__CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on PowerPC and PowerPC-64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00386">386</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a8ef26827072113945e44a7895f63ff35"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8ef26827072113945e44a7895f63ff35">◆ </a></span>HasSHA1()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSHA1 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if an ARM processor has <a class="el" href="class_s_h_a1.html" title="SHA-1 message digest. ">SHA1</a> available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of <a class="el" href="class_s_h_a1.html" title="SHA-1 message digest. ">SHA1</a> at runtime, false otherwise.</dd></dl>
<p><a class="el" href="class_s_h_a1.html" title="SHA-1 message digest. ">SHA1</a> is part of the optional Crypto extensions on Aarch32 and Aarch64. They are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-march=armv8-a+crypto</code>; while Apple requires <code>-arch arm64</code>. Also see ARM's <code>__ARM_FEATURE_CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on ARM-32, Aarch32 and Aarch64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00405">405</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a2564411b398029e7201a48469e30c9bf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2564411b398029e7201a48469e30c9bf">◆ </a></span>HasSHA2()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSHA2 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if an ARM processor has SHA2 available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of SHA2 at runtime, false otherwise.</dd></dl>
<p>SHA2 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-march=armv8-a+crypto</code>; while Apple requires <code>-arch arm64</code>. Also see ARM's <code>__ARM_FEATURE_CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on ARM-32, Aarch32 and Aarch64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00424">424</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a0e0902fb52a61c2c0845be848934f6b3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0e0902fb52a61c2c0845be848934f6b3">◆ </a></span>HasAltivec()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasAltivec </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if a PowerPC processor has Altivec available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of Altivec at runtime, false otherwise.</dd></dl>
<p>Altivec instructions are available under most modern PowerPCs.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mcpu=power7</code>; while IBM XL C/C++ compilers require <code>-qarch=pwr7 -qaltivec</code>. Also see PowerPC's <code>_ALTIVEC_</code> preprocessor macro.</p>
<p>Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the GNUmakefile sets <code>-DCRYPTOPP_DISABLE_ALTIVEC</code>. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on PowerPC and PowerPC-64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00464">464</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a899003e15d0efcea5e96c40d6ed683f0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a899003e15d0efcea5e96c40d6ed683f0">◆ </a></span>HasPower7()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPower7 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if a PowerPC processor has Power8 available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of Power8 at runtime, false otherwise.</dd></dl>
<p>Altivec instructions are available under most modern PowerPCs.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mcpu=power8</code>; while IBM XL C/C++ compilers require <code>-qarch=pwr8 -qaltivec</code>. Also see PowerPC's <code>_ALTIVEC_</code> preprocessor macro.</p>
<p>Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the GNUmakefile sets <code>-DCRYPTOPP_DISABLE_ALTIVEC</code>. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on PowerPC and PowerPC-64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00481">481</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a4fb317243ae628c4bc9cd264200688ca"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4fb317243ae628c4bc9cd264200688ca">◆ </a></span>HasPower8()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasPower8 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if a PowerPC processor has Power8 available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of Power8 at runtime, false otherwise.</dd></dl>
<p>Altivec instructions are available under most modern PowerPCs.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mcpu=power8</code>; while IBM XL C/C++ compilers require <code>-qarch=pwr8 -qaltivec</code>. Also see PowerPC's <code>_ALTIVEC_</code> preprocessor macro.</p>
<p>Atilvec was first available on Power4 platforms. However Crypto++ releies on unaligned loads and stores which is a Power7 feature. If the platform lacks Power7 extensions, then the GNUmakefile sets <code>-DCRYPTOPP_DISABLE_ALTIVEC</code>. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on PowerPC and PowerPC-64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00498">498</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="aaa3d1639456458a8681d2cddb06d72ee"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aaa3d1639456458a8681d2cddb06d72ee">◆ </a></span>HasSHA256()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSHA256 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if a PowerPC processor has <a class="el" href="class_s_h_a256.html" title="SHA-256 message digest. ">SHA256</a> available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of <a class="el" href="class_s_h_a256.html" title="SHA-256 message digest. ">SHA256</a> at runtime, false otherwise.</dd></dl>
<p>SHA is part of the in-crypto extensions on Power8 and Power9.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mcpu=power8</code>; while IBM XL C/C++ compilers require <code>-qarch=pwr8 -qaltivec</code>. Also see PowerPC's <code>__CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on PowerPC and PowerPC-64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00526">526</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
<a id="a1d287c17e472e6d8e0116647786d49f3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1d287c17e472e6d8e0116647786d49f3">◆ </a></span>HasSHA512()</h2>
<div class="memitem">
<div class="memproto">
<table class="mlabels">
<tr>
<td class="mlabels-left">
<table class="memname">
<tr>
<td class="memname">bool HasSHA512 </td>
<td>(</td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</td>
<td class="mlabels-right">
<span class="mlabels"><span class="mlabel">inline</span></span> </td>
</tr>
</table>
</div><div class="memdoc">
<p>Determine if a PowerPC processor has <a class="el" href="class_s_h_a512.html" title="SHA-512 message digest. ">SHA512</a> available. </p>
<dl class="section return"><dt>Returns</dt><dd>true if the hardware is capable of <a class="el" href="class_s_h_a512.html" title="SHA-512 message digest. ">SHA512</a> at runtime, false otherwise.</dd></dl>
<p>SHA is part of the in-crypto extensions on Power8 and Power9.</p>
<p>Runtime support requires compile time support. When compiling with GCC, you may need to compile with <code>-mcpu=power8</code>; while IBM XL C/C++ compilers require <code>-qarch=pwr8 -qaltivec</code>. Also see PowerPC's <code>__CRYPTO</code> preprocessor macro. </p><dl class="section note"><dt>Note</dt><dd>This function is only available on PowerPC and PowerPC-64 platforms </dd></dl>
<p class="definition">Definition at line <a class="el" href="cpu_8h_source.html#l00540">540</a> of file <a class="el" href="cpu_8h_source.html">cpu.h</a>.</p>
</div>
</div>
</div><!-- contents -->
<!-- start footer part -->
<hr class="footer"/><address class="footer"><small>
Generated on Sun Sep 16 2018 07:58:09 for Crypto++ by  <a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/>
</a> 1.8.14
</small></address>
</body>
</html>
distrib
>
Mageia
>
7
>
armv7hl
>
media
>
core-release
>
by-pkgid
>
0a67b807a02637f2cae68649d519a89d
>
files
>
2175
