Hisilicon Hip06 Low Pin Count device
  Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
  provides I/O access to some legacy ISA devices.
  Hip06 is based on arm64 architecture where there is no I/O space. So, the
  I/O ports here are not CPU addresses, and there is no 'ranges' property in
  LPC device node.

Required properties:
- compatible:  value should be as follows:
	(a) "hisilicon,hip06-lpc"
	(b) "hisilicon,hip07-lpc"
- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
- reg: base memory range where the LPC register set is mapped.

Note:
  The node name before '@' must be "isa" to represent the binding stick to the
  ISA/EISA binding specification.

Example:

isa@a01b0000 {
	compatible = "hisilicon,hip06-lpc";
	#address-cells = <2>;
	#size-cells = <1>;
	reg = <0x0 0xa01b0000 0x0 0x1000>;

	ipmi0: bt@e4 {
		compatible = "ipmi-bt";
		device_type = "ipmi";
		reg = <0x01 0xe4 0x04>;
	};
};