* Samsung Exynos5433 CMU (Clock Management Units)

The Exynos5433 clock controller generates and supplies clock to various
controllers within the Exynos5433 SoC.

Required Properties:

- compatible: should be one of the following.
  - "samsung,exynos5433-cmu-top"   - clock controller compatible for CMU_TOP
    which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
    domains and bus clocks.
  - "samsung,exynos5433-cmu-cpif"  - clock controller compatible for CMU_CPIF
    which generates clocks for LLI (Low Latency Interface) IP.
  - "samsung,exynos5433-cmu-mif"   - clock controller compatible for CMU_MIF
    which generates clocks for DRAM Memory Controller domain.
  - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
    which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
  - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
    which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
  - "samsung,exynos5433-cmu-fsys"  - clock controller compatible for CMU_FSYS
    which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
  - "samsung,exynos5433-cmu-g2d"   - clock controller compatible for CMU_G2D
    which generates clocks for G2D/MDMA IPs.
  - "samsung,exynos5433-cmu-disp"  - clock controller compatible for CMU_DISP
    which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
  - "samsung,exynos5433-cmu-aud"   - clock controller compatible for CMU_AUD
    which generates clocks for Cortex-A5/BUS/AUDIO clocks.
  - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
    and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
    which generates global data buses clock and global peripheral buses clock.
  - "samsung,exynos5433-cmu-g3d"  - clock controller compatible for CMU_G3D
    which generates clocks for 3D Graphics Engine IP.
  - "samsung,exynos5433-cmu-gscl"  - clock controller compatible for CMU_GSCL
    which generates clocks for GSCALER IPs.
  - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
    which generates clocks for Cortex-A53 Quad-core processor.
  - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
    which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
    L2 cache controller.
  - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
    which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
  - "samsung,exynos5433-cmu-mfc"  - clock controller compatible for CMU_MFC
    which generates clocks for MFC(Multi-Format Codec) IP.
  - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
    which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
  - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
    which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
  - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
    which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
    IPs.
  - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
    which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
  - "samsung,exynos5433-cmu-imem"   - clock controller compatible for CMU_IMEM
    which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

- clocks: list of the clock controller input clock identifiers,
	from common clock bindings. Please refer the next section
	to find the input clocks for a given controller.

- clock-names: list of the clock controller input clock names,
	as described in clock-bindings.txt.

	Input clocks for top clock controller:
		- oscclk
		- sclk_mphy_pll
		- sclk_mfc_pll
		- sclk_bus_pll

	Input clocks for cpif clock controller:
		- oscclk

	Input clocks for mif clock controller:
		- oscclk
		- sclk_mphy_pll

	Input clocks for fsys clock controller:
		- oscclk
		- sclk_ufs_mphy
		- aclk_fsys_200
		- sclk_pcie_100_fsys
		- sclk_ufsunipro_fsys
		- sclk_mmc2_fsys
		- sclk_mmc1_fsys
		- sclk_mmc0_fsys
		- sclk_usbhost30_fsys
		- sclk_usbdrd30_fsys

	Input clocks for g2d clock controller:
		- oscclk
		- aclk_g2d_266
		- aclk_g2d_400

	Input clocks for disp clock controller:
		- oscclk
		- sclk_dsim1_disp
		- sclk_dsim0_disp
		- sclk_dsd_disp
		- sclk_decon_tv_eclk_disp
		- sclk_decon_vclk_disp
		- sclk_decon_eclk_disp
		- sclk_decon_tv_vclk_disp
		- aclk_disp_333

	Input clocks for audio clock controller:
		- oscclk
		- fout_aud_pll

	Input clocks for bus0 clock controller:
		- aclk_bus0_400

	Input clocks for bus1 clock controller:
		- aclk_bus1_400

	Input clocks for bus2 clock controller:
		- oscclk
		- aclk_bus2_400

	Input clocks for g3d clock controller:
		- oscclk
		- aclk_g3d_400

	Input clocks for gscl clock controller:
		- oscclk
		- aclk_gscl_111
		- aclk_gscl_333

	Input clocks for apollo clock controller:
		- oscclk
		- sclk_bus_pll_apollo

	Input clocks for atlas clock controller:
		- oscclk
		- sclk_bus_pll_atlas

	Input clocks for mscl clock controller:
		- oscclk
		- sclk_jpeg_mscl
		- aclk_mscl_400

	Input clocks for mfc clock controller:
		- oscclk
		- aclk_mfc_400

	Input clocks for hevc clock controller:
		- oscclk
		- aclk_hevc_400

	Input clocks for isp clock controller:
		- oscclk
		- aclk_isp_dis_400
		- aclk_isp_400

	Input clocks for cam0 clock controller:
		- oscclk
		- aclk_cam0_333
		- aclk_cam0_400
		- aclk_cam0_552

	Input clocks for cam1 clock controller:
		- oscclk
		- sclk_isp_uart_cam1
		- sclk_isp_spi1_cam1
		- sclk_isp_spi0_cam1
		- aclk_cam1_333
		- aclk_cam1_400
		- aclk_cam1_552

	Input clocks for imem clock controller:
		- oscclk
		- aclk_imem_sssx_266
		- aclk_imem_266
		- aclk_imem_200

Optional properties:
  - power-domains: a phandle to respective power domain node as described by
	generic PM domain bindings (see power/power_domain.txt for more
	information).

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.

All available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos5433.h header and can be used in device
tree sources.

Example 1: Examples of 'oscclk' source clock node are listed below.

	xxti: xxti {
		compatible = "fixed-clock";
		clock-output-names = "oscclk";
		#clock-cells = <0>;
	};

Example 2: Examples of clock controller nodes are listed below.

	cmu_top: clock-controller@10030000 {
		compatible = "samsung,exynos5433-cmu-top";
		reg = <0x10030000 0x0c04>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"sclk_mphy_pll",
			"sclk_mfc_pll",
			"sclk_bus_pll";
		clocks = <&xxti>,
		       <&cmu_cpif CLK_SCLK_MPHY_PLL>,
		       <&cmu_mif CLK_SCLK_MFC_PLL>,
		       <&cmu_mif CLK_SCLK_BUS_PLL>;
	};

	cmu_cpif: clock-controller@10fc0000 {
		compatible = "samsung,exynos5433-cmu-cpif";
		reg = <0x10fc0000 0x0c04>;
		#clock-cells = <1>;

		clock-names = "oscclk";
		clocks = <&xxti>;
	};

	cmu_mif: clock-controller@105b0000 {
		compatible = "samsung,exynos5433-cmu-mif";
		reg = <0x105b0000 0x100c>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"sclk_mphy_pll";
		clocks = <&xxti>,
		       <&cmu_cpif CLK_SCLK_MPHY_PLL>;
	};

	cmu_peric: clock-controller@14c80000 {
		compatible = "samsung,exynos5433-cmu-peric";
		reg = <0x14c80000 0x0b08>;
		#clock-cells = <1>;
	};

	cmu_peris: clock-controller@10040000 {
		compatible = "samsung,exynos5433-cmu-peris";
		reg = <0x10040000 0x0b20>;
		#clock-cells = <1>;
	};

	cmu_fsys: clock-controller@156e0000 {
		compatible = "samsung,exynos5433-cmu-fsys";
		reg = <0x156e0000 0x0b04>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"sclk_ufs_mphy",
			"aclk_fsys_200",
			"sclk_pcie_100_fsys",
			"sclk_ufsunipro_fsys",
			"sclk_mmc2_fsys",
			"sclk_mmc1_fsys",
			"sclk_mmc0_fsys",
			"sclk_usbhost30_fsys",
			"sclk_usbdrd30_fsys";
		clocks = <&xxti>,
		       <&cmu_cpif CLK_SCLK_UFS_MPHY>,
		       <&cmu_top CLK_ACLK_FSYS_200>,
		       <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
		       <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
		       <&cmu_top CLK_SCLK_MMC2_FSYS>,
		       <&cmu_top CLK_SCLK_MMC1_FSYS>,
		       <&cmu_top CLK_SCLK_MMC0_FSYS>,
		       <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
		       <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
	};

	cmu_g2d: clock-controller@12460000 {
		compatible = "samsung,exynos5433-cmu-g2d";
		reg = <0x12460000 0x0b08>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"aclk_g2d_266",
			"aclk_g2d_400";
		clocks = <&xxti>,
		       <&cmu_top CLK_ACLK_G2D_266>,
		       <&cmu_top CLK_ACLK_G2D_400>;
		power-domains = <&pd_g2d>;
	};

	cmu_disp: clock-controller@13b90000 {
		compatible = "samsung,exynos5433-cmu-disp";
		reg = <0x13b90000 0x0c04>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"sclk_dsim1_disp",
			"sclk_dsim0_disp",
			"sclk_dsd_disp",
			"sclk_decon_tv_eclk_disp",
			"sclk_decon_vclk_disp",
			"sclk_decon_eclk_disp",
			"sclk_decon_tv_vclk_disp",
			"aclk_disp_333";
		clocks = <&xxti>,
		       <&cmu_mif CLK_SCLK_DSIM1_DISP>,
		       <&cmu_mif CLK_SCLK_DSIM0_DISP>,
		       <&cmu_mif CLK_SCLK_DSD_DISP>,
		       <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
		       <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
		       <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
		       <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
		       <&cmu_mif CLK_ACLK_DISP_333>;
		power-domains = <&pd_disp>;
	};

	cmu_aud: clock-controller@114c0000 {
		compatible = "samsung,exynos5433-cmu-aud";
		reg = <0x114c0000 0x0b04>;
		#clock-cells = <1>;

		clock-names = "oscclk", "fout_aud_pll";
		clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
		power-domains = <&pd_aud>;
	};

	cmu_bus0: clock-controller@13600000 {
		compatible = "samsung,exynos5433-cmu-bus0";
		reg = <0x13600000 0x0b04>;
		#clock-cells = <1>;

		clock-names = "aclk_bus0_400";
		clocks = <&cmu_top CLK_ACLK_BUS0_400>;
	};

	cmu_bus1: clock-controller@14800000 {
		compatible = "samsung,exynos5433-cmu-bus1";
		reg = <0x14800000 0x0b04>;
		#clock-cells = <1>;

		clock-names = "aclk_bus1_400";
		clocks = <&cmu_top CLK_ACLK_BUS1_400>;
	};

	cmu_bus2: clock-controller@13400000 {
		compatible = "samsung,exynos5433-cmu-bus2";
		reg = <0x13400000 0x0b04>;
		#clock-cells = <1>;

		clock-names = "oscclk", "aclk_bus2_400";
		clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
	};

	cmu_g3d: clock-controller@14aa0000 {
		compatible = "samsung,exynos5433-cmu-g3d";
		reg = <0x14aa0000 0x1000>;
		#clock-cells = <1>;

		clock-names = "oscclk", "aclk_g3d_400";
		clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
		power-domains = <&pd_g3d>;
	};

	cmu_gscl: clock-controller@13cf0000 {
		compatible = "samsung,exynos5433-cmu-gscl";
		reg = <0x13cf0000 0x0b10>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"aclk_gscl_111",
			"aclk_gscl_333";
		clocks = <&xxti>,
			<&cmu_top CLK_ACLK_GSCL_111>,
			<&cmu_top CLK_ACLK_GSCL_333>;
		power-domains = <&pd_gscl>;
	};

	cmu_apollo: clock-controller@11900000 {
		compatible = "samsung,exynos5433-cmu-apollo";
		reg = <0x11900000 0x1088>;
		#clock-cells = <1>;

		clock-names = "oscclk", "sclk_bus_pll_apollo";
		clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
	};

	cmu_atlas: clock-controller@11800000 {
		compatible = "samsung,exynos5433-cmu-atlas";
		reg = <0x11800000 0x1088>;
		#clock-cells = <1>;

		clock-names = "oscclk", "sclk_bus_pll_atlas";
		clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
	};

	cmu_mscl: clock-controller@105d0000 {
		compatible = "samsung,exynos5433-cmu-mscl";
		reg = <0x105d0000 0x0b10>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"sclk_jpeg_mscl",
			"aclk_mscl_400";
		clocks = <&xxti>,
		       <&cmu_top CLK_SCLK_JPEG_MSCL>,
		       <&cmu_top CLK_ACLK_MSCL_400>;
		power-domains = <&pd_mscl>;
	};

	cmu_mfc: clock-controller@15280000 {
		compatible = "samsung,exynos5433-cmu-mfc";
		reg = <0x15280000 0x0b08>;
		#clock-cells = <1>;

		clock-names = "oscclk", "aclk_mfc_400";
		clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
		power-domains = <&pd_mfc>;
	};

	cmu_hevc: clock-controller@14f80000 {
		compatible = "samsung,exynos5433-cmu-hevc";
		reg = <0x14f80000 0x0b08>;
		#clock-cells = <1>;

		clock-names = "oscclk", "aclk_hevc_400";
		clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
		power-domains = <&pd_hevc>;
	};

	cmu_isp: clock-controller@146d0000 {
		compatible = "samsung,exynos5433-cmu-isp";
		reg = <0x146d0000 0x0b0c>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"aclk_isp_dis_400",
			"aclk_isp_400";
		clocks = <&xxti>,
		       <&cmu_top CLK_ACLK_ISP_DIS_400>,
		       <&cmu_top CLK_ACLK_ISP_400>;
		power-domains = <&pd_isp>;
	};

	cmu_cam0: clock-controller@120d0000 {
		compatible = "samsung,exynos5433-cmu-cam0";
		reg = <0x120d0000 0x0b0c>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"aclk_cam0_333",
			"aclk_cam0_400",
			"aclk_cam0_552";
		clocks = <&xxti>,
		       <&cmu_top CLK_ACLK_CAM0_333>,
		       <&cmu_top CLK_ACLK_CAM0_400>,
		       <&cmu_top CLK_ACLK_CAM0_552>;
		power-domains = <&pd_cam0>;
	};

	cmu_cam1: clock-controller@145d0000 {
		compatible = "samsung,exynos5433-cmu-cam1";
		reg = <0x145d0000 0x0b08>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"sclk_isp_uart_cam1",
			"sclk_isp_spi1_cam1",
			"sclk_isp_spi0_cam1",
			"aclk_cam1_333",
			"aclk_cam1_400",
			"aclk_cam1_552";
		clocks = <&xxti>,
		       <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
		       <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
		       <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
		       <&cmu_top CLK_ACLK_CAM1_333>,
		       <&cmu_top CLK_ACLK_CAM1_400>,
		       <&cmu_top CLK_ACLK_CAM1_552>;
		power-domains = <&pd_cam1>;
	};

	cmu_imem: clock-controller@11060000 {
		compatible = "samsung,exynos5433-cmu-imem";
		reg = <0x11060000 0x1000>;
		#clock-cells = <1>;

		clock-names = "oscclk",
			"aclk_imem_sssx_266",
			"aclk_imem_266",
			"aclk_imem_200";
		clocks = <&xxti>,
			<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
			<&cmu_top CLK_DIV_ACLK_IMEM_266>,
			<&cmu_top CLK_DIV_ACLK_IMEM_200>;
	};

Example 3: UART controller node that consumes the clock generated by the clock
	   controller.

	serial_0: serial@14c10000 {
		compatible = "samsung,exynos5433-uart";
		reg = <0x14C10000 0x100>;
		interrupts = <0 421 0>;
		clocks = <&cmu_peric CLK_PCLK_UART0>,
			 <&cmu_peric CLK_SCLK_UART0>;
		clock-names = "uart", "clk_uart_baud0";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_bus>;
	};