* Rockchip rk3399 DMC (Dynamic Memory Controller) device

Required properties:
- compatible:		 Must be "rockchip,rk3399-dmc".
- devfreq-events:	 Node to get DDR loading, Refer to
			 Documentation/devicetree/bindings/devfreq/event/
			 rockchip-dfi.txt
- clocks:		 Phandles for clock specified in "clock-names" property
- clock-names :		 The name of clock used by the DFI, must be
			 "pclk_ddr_mon";
- operating-points-v2:	 Refer to Documentation/devicetree/bindings/opp/opp.txt
			 for details.
- center-supply:	 DMC supply node.
- status:		 Marks the node enabled/disabled.

Optional properties:
- interrupts:		 The CPU interrupt number. The interrupt specifier
			 format depends on the interrupt controller.
			 It should be a DCF interrupt. When DDR DVFS finishes
			 a DCF interrupt is triggered.

Following properties relate to DDR timing:

- rockchip,dram_speed_bin :	  Value reference include/dt-bindings/clock/rk3399-ddr.h,
				  it selects the DDR3 cl-trp-trcd type. It must be
				  set according to "Speed Bin" in DDR3 datasheet,
				  DO NOT use a smaller "Speed Bin" than specified
				  for the DDR3 being used.

- rockchip,pd_idle :		  Configure the PD_IDLE value. Defines the
				  power-down idle period in which memories are
				  placed into power-down mode if bus is idle
				  for PD_IDLE DFI clock cycles.

- rockchip,sr_idle :		  Configure the SR_IDLE value. Defines the
				  self-refresh idle period in which memories are
				  placed into self-refresh mode if bus is idle
				  for SR_IDLE * 1024 DFI clock cycles (DFI
				  clocks freq is half of DRAM clock), default
				  value is "0".

- rockchip,sr_mc_gate_idle :	  Defines the memory self-refresh and controller
				  clock gating idle period. Memories are placed
				  into self-refresh mode and memory controller
				  clock arg gating started if bus is idle for
				  sr_mc_gate_idle*1024 DFI clock cycles.

- rockchip,srpd_lite_idle :	  Defines the self-refresh power down idle
				  period in which memories are placed into
				  self-refresh power down mode if bus is idle
				  for srpd_lite_idle * 1024 DFI clock cycles.
				  This parameter is for LPDDR4 only.

- rockchip,standby_idle :	  Defines the standby idle period in which
				  memories are placed into self-refresh mode.
				  The controller, pi, PHY and DRAM clock will
				  be gated if bus is idle for standby_idle * DFI
				  clock cycles.

- rockchip,dram_dll_dis_freq :	  Defines the DDR3 DLL bypass frequency in MHz.
				  When DDR frequency is less than DRAM_DLL_DISB_FREQ,
				  DDR3 DLL will be bypassed. Note: if DLL was bypassed,
				  the odt will also stop working.

- rockchip,phy_dll_dis_freq :	  Defines the PHY dll bypass frequency in
				  MHz (Mega Hz). When DDR frequency is less than
				  DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
				  Note: PHY DLL and PHY ODT are independent.

- rockchip,ddr3_odt_dis_freq :	  When the DRAM type is DDR3, this parameter defines
				  the ODT disable frequency in MHz (Mega Hz).
				  when the DDR frequency is  less then ddr3_odt_dis_freq,
				  the ODT on the DRAM side and controller side are
				  both disabled.

- rockchip,ddr3_drv :		  When the DRAM type is DDR3, this parameter defines
				  the DRAM side driver strength in ohms. Default
				  value is DDR3_DS_40ohm.

- rockchip,ddr3_odt :		  When the DRAM type is DDR3, this parameter defines
				  the DRAM side ODT strength in ohms. Default value
				  is DDR3_ODT_120ohm.

- rockchip,phy_ddr3_ca_drv :	  When the DRAM type is DDR3, this parameter defines
				  the phy side CA line (incluing command line,
				  address line and clock line) driver strength.
				  Default value is PHY_DRV_ODT_40.

- rockchip,phy_ddr3_dq_drv :	  When the DRAM type is DDR3, this parameter defines
				  the PHY side DQ line (including DQS/DQ/DM line)
				  driver strength. Default value is PHY_DRV_ODT_40.

- rockchip,phy_ddr3_odt : 	  When the DRAM type is DDR3, this parameter defines
				  the PHY side ODT strength. Default value is
				  PHY_DRV_ODT_240.

- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
				  then ODT disable frequency in MHz (Mega Hz).
				  When DDR frequency is less then ddr3_odt_dis_freq,
				  the ODT on the DRAM side and controller side are
				  both disabled.

- rockchip,lpddr3_drv :		  When the DRAM type is LPDDR3, this parameter defines
				  the DRAM side driver strength in ohms. Default
				  value is LP3_DS_34ohm.

- rockchip,lpddr3_odt :		  When the DRAM type is LPDDR3, this parameter defines
				  the DRAM side ODT strength in ohms. Default value
				  is LP3_ODT_240ohm.

- rockchip,phy_lpddr3_ca_drv :	  When the DRAM type is LPDDR3, this parameter defines
				  the PHY side CA line (including command line,
				  address line and clock line) driver strength.
				  Default value is PHY_DRV_ODT_40.

- rockchip,phy_lpddr3_dq_drv :	  When the DRAM type is LPDDR3, this parameter defines
				  the PHY side DQ line (including DQS/DQ/DM line)
				  driver strength. Default value is
				  PHY_DRV_ODT_40.

- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define
				  the phy side odt strength, default value is
				  PHY_DRV_ODT_240.

- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
				  defines the ODT disable frequency in
				  MHz (Mega Hz). When the DDR frequency is less then
				  ddr3_odt_dis_freq, the ODT on the DRAM side and
				  controller side are both disabled.

- rockchip,lpddr4_drv :		  When the DRAM type is LPDDR4, this parameter defines
				  the DRAM side driver strength in ohms. Default
				  value is LP4_PDDS_60ohm.

- rockchip,lpddr4_dq_odt : 	  When the DRAM type is LPDDR4, this parameter defines
				  the DRAM side ODT on DQS/DQ line strength in ohms.
				  Default value is LP4_DQ_ODT_40ohm.

- rockchip,lpddr4_ca_odt :	  When the DRAM type is LPDDR4, this parameter defines
				  the DRAM side ODT on CA line strength in ohms.
				  Default value is LP4_CA_ODT_40ohm.

- rockchip,phy_lpddr4_ca_drv :	  When the DRAM type is LPDDR4, this parameter defines
				  the PHY side CA line (including command address
				  line) driver strength. Default value is
				  PHY_DRV_ODT_40.

- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
				  the PHY side clock line and CS line driver
				  strength. Default value is PHY_DRV_ODT_80.

- rockchip,phy_lpddr4_dq_drv :	  When the DRAM type is LPDDR4, this parameter defines
				  the PHY side DQ line (including DQS/DQ/DM line)
				  driver strength. Default value is PHY_DRV_ODT_80.

- rockchip,phy_lpddr4_odt :	  When the DRAM type is LPDDR4, this parameter defines
				  the PHY side ODT strength. Default value is
				  PHY_DRV_ODT_60.

Example:
	dmc_opp_table: dmc_opp_table {
		compatible = "operating-points-v2";

		opp00 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <900000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <666000000>;
			opp-microvolt = <900000>;
		};
	};

	dmc: dmc {
		compatible = "rockchip,rk3399-dmc";
		devfreq-events = <&dfi>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_DDRCLK>;
		clock-names = "dmc_clk";
		operating-points-v2 = <&dmc_opp_table>;
		center-supply = <&ppvar_centerlogic>;
		upthreshold = <15>;
		downdifferential = <10>;
		rockchip,ddr3_speed_bin = <21>;
		rockchip,pd_idle = <0x40>;
		rockchip,sr_idle = <0x2>;
		rockchip,sr_mc_gate_idle = <0x3>;
		rockchip,srpd_lite_idle	= <0x4>;
		rockchip,standby_idle = <0x2000>;
		rockchip,dram_dll_dis_freq = <300>;
		rockchip,phy_dll_dis_freq = <125>;
		rockchip,auto_pd_dis_freq = <666>;
		rockchip,ddr3_odt_dis_freq = <333>;
		rockchip,ddr3_drv = <DDR3_DS_40ohm>;
		rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
		rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
		rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
		rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
		rockchip,lpddr3_odt_dis_freq = <333>;
		rockchip,lpddr3_drv = <LP3_DS_34ohm>;
		rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
		rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
		rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
		rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
		rockchip,lpddr4_odt_dis_freq = <333>;
		rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
		rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
		rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
		rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
		rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
		rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
		rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
	};