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<div class="section" id="user-guide-for-amdgpu-backend">
<h1>User Guide for AMDGPU Backend<a class="headerlink" href="#user-guide-for-amdgpu-backend" title="Permalink to this headline">¶</a></h1>
<div class="contents local topic" id="contents">
<ul class="simple">
<li><a class="reference internal" href="#introduction" id="id46">Introduction</a></li>
<li><a class="reference internal" href="#llvm" id="id47">LLVM</a><ul>
<li><a class="reference internal" href="#target-triples" id="id48">Target Triples</a></li>
<li><a class="reference internal" href="#processors" id="id49">Processors</a></li>
<li><a class="reference internal" href="#target-features" id="id50">Target Features</a></li>
<li><a class="reference internal" href="#address-spaces" id="id51">Address Spaces</a></li>
<li><a class="reference internal" href="#memory-scopes" id="id52">Memory Scopes</a></li>
<li><a class="reference internal" href="#amdgpu-intrinsics" id="id53">AMDGPU Intrinsics</a></li>
<li><a class="reference internal" href="#amdgpu-attributes" id="id54">AMDGPU Attributes</a></li>
</ul>
</li>
<li><a class="reference internal" href="#code-object" id="id55">Code Object</a><ul>
<li><a class="reference internal" href="#header" id="id56">Header</a></li>
<li><a class="reference internal" href="#sections" id="id57">Sections</a></li>
<li><a class="reference internal" href="#note-records" id="id58">Note Records</a><ul>
<li><a class="reference internal" href="#code-object-v2-note-records-mattr-code-object-v3" id="id59">Code Object V2 Note Records (-mattr=-code-object-v3)</a></li>
<li><a class="reference internal" href="#code-object-v3-note-records-mattr-code-object-v3" id="id60">Code Object V3 Note Records (-mattr=+code-object-v3)</a></li>
</ul>
</li>
<li><a class="reference internal" href="#symbols" id="id61">Symbols</a></li>
<li><a class="reference internal" href="#relocation-records" id="id62">Relocation Records</a></li>
<li><a class="reference internal" href="#dwarf" id="id63">DWARF</a><ul>
<li><a class="reference internal" href="#address-space-mapping" id="id64">Address Space Mapping</a></li>
<li><a class="reference internal" href="#register-mapping" id="id65">Register Mapping</a></li>
<li><a class="reference internal" href="#source-text" id="id66">Source Text</a></li>
</ul>
</li>
</ul>
</li>
<li><a class="reference internal" href="#code-conventions" id="id67">Code Conventions</a><ul>
<li><a class="reference internal" href="#amdhsa" id="id68">AMDHSA</a><ul>
<li><a class="reference internal" href="#code-object-target-identification" id="id69">Code Object Target Identification</a></li>
<li><a class="reference internal" href="#code-object-metadata" id="id70">Code Object Metadata</a><ul>
<li><a class="reference internal" href="#code-object-v2-metadata-mattr-code-object-v3" id="id71">Code Object V2 Metadata (-mattr=-code-object-v3)</a></li>
<li><a class="reference internal" href="#code-object-v3-metadata-mattr-code-object-v3" id="id72">Code Object V3 Metadata (-mattr=+code-object-v3)</a></li>
</ul>
</li>
<li><a class="reference internal" href="#kernel-dispatch" id="id73">Kernel Dispatch</a></li>
<li><a class="reference internal" href="#memory-spaces" id="id74">Memory Spaces</a></li>
<li><a class="reference internal" href="#image-and-samplers" id="id75">Image and Samplers</a></li>
<li><a class="reference internal" href="#hsa-signals" id="id76">HSA Signals</a></li>
<li><a class="reference internal" href="#hsa-aql-queue" id="id77">HSA AQL Queue</a></li>
<li><a class="reference internal" href="#kernel-descriptor" id="id78">Kernel Descriptor</a><ul>
<li><a class="reference internal" href="#kernel-descriptor-for-gfx6-gfx9" id="id79">Kernel Descriptor for GFX6-GFX9</a></li>
</ul>
</li>
<li><a class="reference internal" href="#initial-kernel-execution-state" id="id80">Initial Kernel Execution State</a></li>
<li><a class="reference internal" href="#kernel-prolog" id="id81">Kernel Prolog</a><ul>
<li><a class="reference internal" href="#m0" id="id82">M0</a></li>
<li><a class="reference internal" href="#flat-scratch" id="id83">Flat Scratch</a></li>
</ul>
</li>
<li><a class="reference internal" href="#memory-model" id="id84">Memory Model</a></li>
<li><a class="reference internal" href="#trap-handler-abi" id="id85">Trap Handler ABI</a></li>
</ul>
</li>
<li><a class="reference internal" href="#amdpal" id="id86">AMDPAL</a><ul>
<li><a class="reference internal" href="#user-data" id="id87">User Data</a></li>
<li><a class="reference internal" href="#compute-user-data" id="id88">Compute User Data</a></li>
<li><a class="reference internal" href="#graphics-user-data" id="id89">Graphics User Data</a></li>
<li><a class="reference internal" href="#global-internal-table" id="id90">Global Internal Table</a></li>
</ul>
</li>
<li><a class="reference internal" href="#unspecified-os" id="id91">Unspecified OS</a><ul>
<li><a class="reference internal" href="#id38" id="id92">Trap Handler ABI</a></li>
</ul>
</li>
</ul>
</li>
<li><a class="reference internal" href="#source-languages" id="id93">Source Languages</a><ul>
<li><a class="reference internal" href="#opencl" id="id94">OpenCL</a></li>
<li><a class="reference internal" href="#hcc" id="id95">HCC</a></li>
<li><a class="reference internal" href="#assembler" id="id96">Assembler</a><ul>
<li><a class="reference internal" href="#instructions" id="id97">Instructions</a></li>
<li><a class="reference internal" href="#operands" id="id98">Operands</a></li>
<li><a class="reference internal" href="#modifiers" id="id99">Modifiers</a></li>
<li><a class="reference internal" href="#instruction-examples" id="id100">Instruction Examples</a><ul>
<li><a class="reference internal" href="#ds" id="id101">DS</a></li>
<li><a class="reference internal" href="#flat" id="id102">FLAT</a></li>
<li><a class="reference internal" href="#mubuf" id="id103">MUBUF</a></li>
<li><a class="reference internal" href="#smrd-smem" id="id104">SMRD/SMEM</a></li>
<li><a class="reference internal" href="#sop1" id="id105">SOP1</a></li>
<li><a class="reference internal" href="#sop2" id="id106">SOP2</a></li>
<li><a class="reference internal" href="#sopc" id="id107">SOPC</a></li>
<li><a class="reference internal" href="#sopp" id="id108">SOPP</a></li>
<li><a class="reference internal" href="#valu" id="id109">VALU</a></li>
</ul>
</li>
<li><a class="reference internal" href="#hsa-code-object-directives" id="id110">HSA Code Object Directives</a><ul>
<li><a class="reference internal" href="#hsa-code-object-version-major-minor" id="id111">.hsa_code_object_version major, minor</a></li>
<li><a class="reference internal" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" id="id112">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a></li>
<li><a class="reference internal" href="#amdgpu-hsa-kernel-name" id="id113">.amdgpu_hsa_kernel (name)</a></li>
<li><a class="reference internal" href="#amd-kernel-code-t" id="id114">.amd_kernel_code_t</a></li>
</ul>
</li>
<li><a class="reference internal" href="#predefined-symbols-mattr-code-object-v3" id="id115">Predefined Symbols (-mattr=+code-object-v3)</a><ul>
<li><a class="reference internal" href="#amdgcn-gfx-generation-number" id="id116">.amdgcn.gfx_generation_number</a></li>
<li><a class="reference internal" href="#amdgcn-next-free-vgpr" id="id117">.amdgcn.next_free_vgpr</a></li>
<li><a class="reference internal" href="#amdgcn-next-free-sgpr" id="id118">.amdgcn.next_free_sgpr</a></li>
</ul>
</li>
<li><a class="reference internal" href="#code-object-directives-mattr-code-object-v3" id="id119">Code Object Directives (-mattr=+code-object-v3)</a><ul>
<li><a class="reference internal" href="#amdgcn-target-target" id="id120">.amdgcn_target <target></a></li>
<li><a class="reference internal" href="#amdhsa-kernel-name" id="id121">.amdhsa_kernel <name></a></li>
<li><a class="reference internal" href="#amdgpu-metadata" id="id122">.amdgpu_metadata</a></li>
</ul>
</li>
<li><a class="reference internal" href="#example-hsa-source-code-mattr-code-object-v3" id="id123">Example HSA Source Code (-mattr=+code-object-v3)</a></li>
</ul>
</li>
</ul>
</li>
<li><a class="reference internal" href="#additional-documentation" id="id124">Additional Documentation</a></li>
</ul>
</div>
<div class="section" id="introduction">
<h2><a class="toc-backref" href="#id46">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
<p>The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the
R600 family up until the current GCN families. It lives in the
<code class="docutils literal notranslate"><span class="pre">lib/Target/AMDGPU</span></code> directory.</p>
</div>
<div class="section" id="llvm">
<h2><a class="toc-backref" href="#id47">LLVM</a><a class="headerlink" href="#llvm" title="Permalink to this headline">¶</a></h2>
<div class="section" id="target-triples">
<span id="amdgpu-target-triples"></span><h3><a class="toc-backref" href="#id48">Target Triples</a><a class="headerlink" href="#target-triples" title="Permalink to this headline">¶</a></h3>
<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-target</span> <span class="pre"><Architecture>-<Vendor>-<OS>-<Environment></span></code> option to
specify the target triple:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-architecture-table">
<caption><span class="caption-text">AMDGPU Architectures</span><a class="headerlink" href="#amdgpu-architecture-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="16%" />
<col width="84%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Architecture</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>AMD GPUs GCN GFX6 onwards for graphics and compute shaders.</td>
</tr>
</tbody>
</table>
<table border="1" class="docutils" id="amdgpu-vendor-table">
<caption><span class="caption-text">AMDGPU Vendors</span><a class="headerlink" href="#amdgpu-vendor-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="16%" />
<col width="84%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Vendor</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">amd</span></code></td>
<td>Can be used for all AMD GPU usage.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">mesa3d</span></code></td>
<td>Can be used if the OS is <code class="docutils literal notranslate"><span class="pre">mesa3d</span></code>.</td>
</tr>
</tbody>
</table>
<table border="1" class="docutils" id="amdgpu-os-table">
<caption><span class="caption-text">AMDGPU Operating Systems</span><a class="headerlink" href="#amdgpu-os-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="19%" />
<col width="81%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">OS</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><em><empty></em></td>
<td>Defaults to the <em>unknown</em> OS.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">amdhsa</span></code></td>
<td>Compute kernels executed on HSA <a class="reference internal" href="#hsa" id="id1">[HSA]</a> compatible runtimes
such as AMD’s ROCm <a class="reference internal" href="#amd-rocm" id="id2">[AMD-ROCm]</a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">amdpal</span></code></td>
<td>Graphic shaders and compute kernels executed on AMD PAL
runtime.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">mesa3d</span></code></td>
<td>Graphic shaders and compute kernels executed on Mesa 3D
runtime.</td>
</tr>
</tbody>
</table>
<table border="1" class="docutils" id="amdgpu-environment-table">
<caption><span class="caption-text">AMDGPU Environments</span><a class="headerlink" href="#amdgpu-environment-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="16%" />
<col width="84%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Environment</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><em><empty></em></td>
<td>Default.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="processors">
<span id="amdgpu-processors"></span><h3><a class="toc-backref" href="#id49">Processors</a><a class="headerlink" href="#processors" title="Permalink to this headline">¶</a></h3>
<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-mcpu</span> <span class="pre"><Processor></span></code> option to specify the AMD GPU processor. The
names from both the <em>Processor</em> and <em>Alternative Processor</em> can be used.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-processor-table">
<caption><span class="caption-text">AMDGPU Processors</span><a class="headerlink" href="#amdgpu-processor-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="13%" />
<col width="18%" />
<col width="15%" />
<col width="6%" />
<col width="12%" />
<col width="9%" />
<col width="27%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Processor</th>
<th class="head">Alternative
Processor</th>
<th class="head">Target
Triple
Architecture</th>
<th class="head">dGPU/
APU</th>
<th class="head">Target
Features
Supported
[Default]</th>
<th class="head">ROCm
Support</th>
<th class="head">Example
Products</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td colspan="7"><strong>Radeon HD 2000/3000 Series (R600)</strong> <a class="reference internal" href="#amd-radeon-hd-2000-3000" id="id3">[AMD-RADEON-HD-2000-3000]</a></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">r630</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">rs880</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv670</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td colspan="7"><strong>Radeon HD 4000 Series (R700)</strong> <a class="reference internal" href="#amd-radeon-hd-4000" id="id4">[AMD-RADEON-HD-4000]</a></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv710</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">rv730</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv770</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td colspan="7"><strong>Radeon HD 5000 Series (Evergreen)</strong> <a class="reference internal" href="#amd-radeon-hd-5000" id="id5">[AMD-RADEON-HD-5000]</a></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">cedar</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">cypress</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">juniper</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">redwood</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">sumo</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td colspan="7"><strong>Radeon HD 6000 Series (Northern Islands)</strong> <a class="reference internal" href="#amd-radeon-hd-6000" id="id6">[AMD-RADEON-HD-6000]</a></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">barts</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">caicos</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">cayman</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">turks</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td colspan="7"><strong>GCN GFX6 (Southern Islands (SI))</strong> <a class="reference internal" href="#amd-gcn-gfx6" id="id7">[AMD-GCN-GFX6]</a></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx600</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">tahiti</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx601</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">hainan</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">oland</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">pitcairn</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">verde</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td colspan="7"><strong>GCN GFX7 (Sea Islands (CI))</strong> <a class="reference internal" href="#amd-gcn-gfx7" id="id8">[AMD-GCN-GFX7]</a></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx700</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">kaveri</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td> </td>
<td> </td>
<td><ul class="first last simple">
<li>A6-7000</li>
<li>A6 Pro-7050B</li>
<li>A8-7100</li>
<li>A8 Pro-7150B</li>
<li>A10-7300</li>
<li>A10 Pro-7350B</li>
<li>FX-7500</li>
<li>A8-7200P</li>
<li>A10-7400P</li>
<li>FX-7600P</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx701</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">hawaii</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td> </td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>FirePro W8100</li>
<li>FirePro W9100</li>
<li>FirePro S9150</li>
<li>FirePro S9170</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx702</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td> </td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>Radeon R9 290</li>
<li>Radeon R9 290x</li>
<li>Radeon R390</li>
<li>Radeon R390x</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx703</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">kabini</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">mullins</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td> </td>
<td> </td>
<td><ul class="first last simple">
<li>E1-2100</li>
<li>E1-2200</li>
<li>E1-2500</li>
<li>E2-3000</li>
<li>E2-3800</li>
<li>A4-5000</li>
<li>A4-5100</li>
<li>A6-5200</li>
<li>A4 Pro-3340B</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx704</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">bonaire</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td> </td>
<td> </td>
<td><ul class="first last simple">
<li>Radeon HD 7790</li>
<li>Radeon HD 8770</li>
<li>R7 260</li>
<li>R7 260X</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td colspan="7"><strong>GCN GFX8 (Volcanic Islands (VI))</strong> <a class="reference internal" href="#amd-gcn-gfx8" id="id9">[AMD-GCN-GFX8]</a></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx801</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">carrizo</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td> </td>
<td><ul class="first last simple">
<li>A6-8500P</li>
<li>Pro A6-8500B</li>
<li>A8-8600P</li>
<li>Pro A8-8600B</li>
<li>FX-8800P</li>
<li>Pro A12-8800B</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>A10-8700P</li>
<li>Pro A10-8700B</li>
<li>A10-8780P</li>
</ul>
</td>
</tr>
<tr class="row-even"><td></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td> </td>
<td><ul class="first last simple">
<li>A10-9600P</li>
<li>A10-9630P</li>
<li>A12-9700P</li>
<li>A12-9730P</li>
<li>FX-9800P</li>
<li>FX-9830P</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td> </td>
<td><ul class="first last simple">
<li>E2-9010</li>
<li>A6-9210</li>
<li>A9-9410</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx802</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">iceland</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">tonga</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]</li>
</ul>
</td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>FirePro S7150</li>
<li>FirePro S7100</li>
<li>FirePro W7100</li>
<li>Radeon R285</li>
<li>Radeon R9 380</li>
<li>Radeon R9 385</li>
<li>Mobile FirePro
M7170</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx803</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">fiji</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]</li>
</ul>
</td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>Radeon R9 Nano</li>
<li>Radeon R9 Fury</li>
<li>Radeon R9 FuryX</li>
<li>Radeon Pro Duo</li>
<li>FirePro S9300x2</li>
<li>Radeon Instinct MI8</li>
</ul>
</td>
</tr>
<tr class="row-even"><td></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">polaris10</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]</li>
</ul>
</td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>Radeon RX 470</li>
<li>Radeon RX 480</li>
<li>Radeon Instinct MI6</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">polaris11</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]</li>
</ul>
</td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>Radeon RX 460</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx810</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">stoney</span></code></li>
</ul>
</td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td colspan="7"><strong>GCN GFX9</strong> <a class="reference internal" href="#amd-gcn-gfx9" id="id10">[AMD-GCN-GFX9]</a></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx900</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]</li>
</ul>
</td>
<td>ROCm</td>
<td><ul class="first last simple">
<li>Radeon Vega
Frontier Edition</li>
<li>Radeon RX Vega 56</li>
<li>Radeon RX Vega 64</li>
<li>Radeon RX Vega 64
Liquid</li>
<li>Radeon Instinct MI25</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx902</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td> </td>
<td><ul class="first last simple">
<li>Ryzen 3 2200G</li>
<li>Ryzen 5 2400G</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx904</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]</li>
</ul>
</td>
<td> </td>
<td><em>TBA</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx906</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>dGPU</td>
<td><ul class="first last simple">
<li>xnack
[off]
sram-ecc
[on]</li>
</ul>
</td>
<td> </td>
<td><ul class="first last simple">
<li>Radeon Instinct MI50</li>
<li>Radeon Instinct MI60</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx909</span></code></td>
<td> </td>
<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
<td>APU</td>
<td><ul class="first last simple">
<li>xnack
[on]</li>
</ul>
</td>
<td> </td>
<td><em>TBA</em> (Raven Ridge 2)</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="target-features">
<span id="amdgpu-target-features"></span><h3><a class="toc-backref" href="#id50">Target Features</a><a class="headerlink" href="#target-features" title="Permalink to this headline">¶</a></h3>
<p>Target features control how code is generated to support certain
processor specific features. Not all target features are supported by
all processors. The runtime must ensure that the features supported by
the device used to execute the code match the features enabled when
generating the code. A mismatch of features may result in incorrect
execution, or a reduction in performance.</p>
<p>The target features supported by each processor, and the default value
used if not specified explicitly, is listed in
<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</p>
<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-m[no-]<TargetFeature></span></code> option to specify the AMD GPU
target features.</p>
<p>For example:</p>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">-mxnack</span></code></dt>
<dd>Enable the <code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">-mno-xnack</span></code></dt>
<dd><p class="first">Disable the <code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature.</p>
<table border="1" class="last docutils" id="amdgpu-target-feature-table">
<caption><span class="caption-text">AMDGPU Target Features</span><a class="headerlink" href="#amdgpu-target-feature-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="23%" />
<col width="77%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Target Feature</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>-m[no-]xnack</td>
<td><p class="first">Enable/disable generating code that has
memory clauses that are compatible with
having XNACK replay enabled.</p>
<p class="last">This is used for demand paging and page
migration. If XNACK replay is enabled in
the device, then if a page fault occurs
the code may execute incorrectly if the
<code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature is not enabled. Executing
code that has the feature enabled on a
device that does not have XNACK replay
enabled will execute correctly, but may
be less performant than code with the
feature disabled.</p>
</td>
</tr>
<tr class="row-odd"><td>-m[no-]sram-ecc</td>
<td>Enable/disable generating code that assumes SRAM
ECC is enabled/disabled.</td>
</tr>
</tbody>
</table>
</dd>
</dl>
</div>
<div class="section" id="address-spaces">
<span id="amdgpu-address-spaces"></span><h3><a class="toc-backref" href="#id51">Address Spaces</a><a class="headerlink" href="#address-spaces" title="Permalink to this headline">¶</a></h3>
<p>The AMDGPU backend uses the following address space mappings.</p>
<p>The memory space names used in the table, aside from the region memory space, is
from the OpenCL standard.</p>
<p>LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-address-space-mapping-table">
<caption><span class="caption-text">Address Space Mapping</span><a class="headerlink" href="#amdgpu-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="51%" />
<col width="49%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">LLVM Address Space</th>
<th class="head">Memory Space</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>0</td>
<td>Generic (Flat)</td>
</tr>
<tr class="row-odd"><td>1</td>
<td>Global</td>
</tr>
<tr class="row-even"><td>2</td>
<td>Region (GDS)</td>
</tr>
<tr class="row-odd"><td>3</td>
<td>Local (group/LDS)</td>
</tr>
<tr class="row-even"><td>4</td>
<td>Constant</td>
</tr>
<tr class="row-odd"><td>5</td>
<td>Private (Scratch)</td>
</tr>
<tr class="row-even"><td>6</td>
<td>Constant 32-bit</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="memory-scopes">
<span id="amdgpu-memory-scopes"></span><h3><a class="toc-backref" href="#id52">Memory Scopes</a><a class="headerlink" href="#memory-scopes" title="Permalink to this headline">¶</a></h3>
<p>This section provides LLVM memory synchronization scopes supported by the AMDGPU
backend memory model when the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see
<a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a> and <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
<p>The memory model supported is based on the HSA memory model <a class="reference internal" href="#hsa" id="id11">[HSA]</a> which is
based in turn on HRF-indirect with scope inclusion <a class="reference internal" href="#hrf" id="id12">[HRF]</a>. The happens-before
relation is transitive over the synchonizes-with relation independent of scope,
and synchonizes-with allows the memory scope instances to be inclusive (see
table <a class="reference internal" href="#amdgpu-amdhsa-llvm-sync-scopes-table"><span class="std std-ref">AMDHSA LLVM Sync Scopes</span></a>).</p>
<p>This is different to the OpenCL <a class="reference internal" href="#id45" id="id13">[OpenCL]</a> memory model which does not have scope
inclusion and requires the memory scopes to exactly match. However, this
is conservatively correct for OpenCL.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-llvm-sync-scopes-table">
<caption><span class="caption-text">AMDHSA LLVM Sync Scopes</span><a class="headerlink" href="#amdgpu-amdhsa-llvm-sync-scopes-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="22%" />
<col width="78%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">LLVM Sync Scope</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><em>none</em></td>
<td><p class="first">The default: <code class="docutils literal notranslate"><span class="pre">system</span></code>.</p>
<p>Synchronizes with, and participates in modification and
seq_cst total orderings with, other operations (except
image operations) for all address spaces (except private,
or generic that accesses private) provided the other
operation’s sync scope is:</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">system</span></code>.</li>
<li><code class="docutils literal notranslate"><span class="pre">agent</span></code> and executed by a thread on the same agent.</li>
<li><code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a thread in the same
workgroup.</li>
<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the same
wavefront.</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">agent</span></code></td>
<td><p class="first">Synchronizes with, and participates in modification and
seq_cst total orderings with, other operations (except
image operations) for all address spaces (except private,
or generic that accesses private) provided the other
operation’s sync scope is:</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">system</span></code> or <code class="docutils literal notranslate"><span class="pre">agent</span></code> and executed by a thread on the
same agent.</li>
<li><code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a thread in the same
workgroup.</li>
<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the same
wavefront.</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">workgroup</span></code></td>
<td><p class="first">Synchronizes with, and participates in modification and
seq_cst total orderings with, other operations (except
image operations) for all address spaces (except private,
or generic that accesses private) provided the other
operation’s sync scope is:</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">system</span></code>, <code class="docutils literal notranslate"><span class="pre">agent</span></code> or <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a
thread in the same workgroup.</li>
<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the same
wavefront.</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">wavefront</span></code></td>
<td><p class="first">Synchronizes with, and participates in modification and
seq_cst total orderings with, other operations (except
image operations) for all address spaces (except private,
or generic that accesses private) provided the other
operation’s sync scope is:</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">system</span></code>, <code class="docutils literal notranslate"><span class="pre">agent</span></code>, <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> or <code class="docutils literal notranslate"><span class="pre">wavefront</span></code>
and executed by a thread in the same wavefront.</li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">singlethread</span></code></td>
<td>Only synchronizes with, and participates in modification
and seq_cst total orderings with, other operations (except
image operations) running in the same thread for all
address spaces (for example, in signal handlers).</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="amdgpu-intrinsics">
<h3><a class="toc-backref" href="#id53">AMDGPU Intrinsics</a><a class="headerlink" href="#amdgpu-intrinsics" title="Permalink to this headline">¶</a></h3>
<p>The AMDGPU backend implements the following LLVM IR intrinsics.</p>
<p><em>This section is WIP.</em></p>
</div>
<div class="section" id="amdgpu-attributes">
<h3><a class="toc-backref" href="#id54">AMDGPU Attributes</a><a class="headerlink" href="#amdgpu-attributes" title="Permalink to this headline">¶</a></h3>
<p>The AMDGPU backend supports the following LLVM IR attributes.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-llvm-ir-attributes-table">
<caption><span class="caption-text">AMDGPU LLVM IR Attributes</span><a class="headerlink" href="#amdgpu-llvm-ir-attributes-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="36%" />
<col width="64%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">LLVM Attribute</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“amdgpu-flat-work-group-size”=”min,max”</td>
<td>Specify the minimum and maximum flat work group sizes that
will be specified when the kernel is dispatched. Generated
by the <code class="docutils literal notranslate"><span class="pre">amdgpu_flat_work_group_size</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id14">[CLANG-ATTR]</a>.</td>
</tr>
<tr class="row-odd"><td>“amdgpu-implicitarg-num-bytes”=”n”</td>
<td>Number of kernel argument bytes to add to the kernel
argument block size for the implicit arguments. This
varies by OS and language (for OpenCL see
<a class="reference internal" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table"><span class="std std-ref">OpenCL kernel implicit arguments appended for AMDHSA OS</span></a>).</td>
</tr>
<tr class="row-even"><td>“amdgpu-max-work-group-size”=”n”</td>
<td>Specify the maximum work-group size that will be specifed
when the kernel is dispatched.</td>
</tr>
<tr class="row-odd"><td>“amdgpu-num-sgpr”=”n”</td>
<td>Specifies the number of SGPRs to use. Generated by
the <code class="docutils literal notranslate"><span class="pre">amdgpu_num_sgpr</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id15">[CLANG-ATTR]</a>.</td>
</tr>
<tr class="row-even"><td>“amdgpu-num-vgpr”=”n”</td>
<td>Specifies the number of VGPRs to use. Generated by the
<code class="docutils literal notranslate"><span class="pre">amdgpu_num_vgpr</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id16">[CLANG-ATTR]</a>.</td>
</tr>
<tr class="row-odd"><td>“amdgpu-waves-per-eu”=”m,n”</td>
<td>Specify the minimum and maximum number of waves per
execution unit. Generated by the <code class="docutils literal notranslate"><span class="pre">amdgpu_waves_per_eu</span></code>
CLANG attribute <a class="reference internal" href="#clang-attr" id="id17">[CLANG-ATTR]</a>.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="code-object">
<h2><a class="toc-backref" href="#id55">Code Object</a><a class="headerlink" href="#code-object" title="Permalink to this headline">¶</a></h2>
<p>The AMDGPU backend generates a standard ELF <a class="reference internal" href="#elf" id="id18">[ELF]</a> relocatable code object that
can be linked by <code class="docutils literal notranslate"><span class="pre">lld</span></code> to produce a standard ELF shared code object which can
be loaded and executed on an AMDGPU target.</p>
<div class="section" id="header">
<h3><a class="toc-backref" href="#id56">Header</a><a class="headerlink" href="#header" title="Permalink to this headline">¶</a></h3>
<p>The AMDGPU backend uses the following ELF header:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-header-table">
<caption><span class="caption-text">AMDGPU ELF Header</span><a class="headerlink" href="#amdgpu-elf-header-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="38%" />
<col width="62%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Field</th>
<th class="head">Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_CLASS]</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_DATA]</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">ELFDATA2LSB</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_OSABI]</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_ABIVERSION]</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></li>
</ul>
</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_type</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">ET_REL</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code></li>
</ul>
</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_machine</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_entry</span></code></td>
<td>0</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_flags</span></code></td>
<td>See <a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a></td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-header-enumeration-values-table">
<caption><span class="caption-text">AMDGPU ELF Header Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-header-enumeration-values-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="86%" />
<col width="14%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code></td>
<td>224</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code></td>
<td>0</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></td>
<td>64</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></td>
<td>65</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></td>
<td>66</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></td>
<td>1</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></td>
<td>0</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></td>
<td>0</td>
</tr>
</tbody>
</table>
</div></blockquote>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_CLASS]</span></code></dt>
<dd><p class="first">The ELF class is:</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">ELFCLASS32</span></code> for <code class="docutils literal notranslate"><span class="pre">r600</span></code> architecture.</li>
<li><code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code> for <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architecture which only supports 64
bit applications.</li>
</ul>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_DATA]</span></code></dt>
<dd>All AMDGPU targets use <code class="docutils literal notranslate"><span class="pre">ELFDATA2LSB</span></code> for little-endian byte ordering.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_OSABI]</span></code></dt>
<dd><p class="first">One of the following AMD GPU architecture specific OS ABIs
(see <a class="reference internal" href="#amdgpu-os-table"><span class="std std-ref">AMDGPU Operating Systems</span></a>):</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code> for <em>unknown</em> OS.</li>
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code> for <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS.</li>
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code> for <code class="docutils literal notranslate"><span class="pre">amdpal</span></code> OS.</li>
<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code> for <code class="docutils literal notranslate"><span class="pre">mesa3D</span></code> OS.</li>
</ul>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_ABIVERSION]</span></code></dt>
<dd><p class="first">The ABI version of the AMD GPU architecture specific OS ABI to which the code
object conforms:</p>
<ul class="last simple">
<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code> is used to specify the version of AMD HSA
runtime ABI.</li>
<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code> is used to specify the version of AMD PAL
runtime ABI.</li>
<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code> is used to specify the version of AMD MESA
3D runtime ABI.</li>
</ul>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_type</span></code></dt>
<dd><p class="first">Can be one of the following values:</p>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">ET_REL</span></code></dt>
<dd>The type produced by the AMD GPU backend compiler as it is relocatable code
object.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code></dt>
<dd>The type produced by the linker as it is a shared code object.</dd>
</dl>
<p class="last">The AMD HSA runtime loader requires a <code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code> code object.</p>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_machine</span></code></dt>
<dd>The value <code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code> is used for the machine for all processors supported
by the <code class="docutils literal notranslate"><span class="pre">r600</span></code> and <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architectures (see
<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>). The specific processor is specified in the
<code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code> bit field of the <code class="docutils literal notranslate"><span class="pre">e_flags</span></code> (see
<a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a>).</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_entry</span></code></dt>
<dd>The entry point is 0 as the entry points for individual kernels must be
selected in order to invoke them through AQL packets.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">e_flags</span></code></dt>
<dd><p class="first">The AMDGPU backend uses the following ELF header flags:</p>
<table border="1" class="docutils" id="amdgpu-elf-header-e-flags-table">
<caption><span class="caption-text">AMDGPU ELF Header <code class="docutils literal notranslate"><span class="pre">e_flags</span></code></span><a class="headerlink" href="#amdgpu-elf-header-e-flags-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="42%" />
<col width="13%" />
<col width="45%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Value</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td colspan="2"><strong>AMDGPU Processor Flag</strong></td>
<td>See <a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code></td>
<td>0x000000ff</td>
<td>AMDGPU processor selection
mask for
<code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_xxx</span></code> values
defined in
<a class="reference internal" href="#amdgpu-ef-amdgpu-mach-table"><span class="std std-ref">AMDGPU EF_AMDGPU_MACH Values</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_XNACK</span></code></td>
<td>0x00000100</td>
<td>Indicates if the <code class="docutils literal notranslate"><span class="pre">xnack</span></code>
target feature is
enabled for all code
contained in the code object.
If the processor
does not support the
<code class="docutils literal notranslate"><span class="pre">xnack</span></code> target
feature then must
be 0.
See
<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_SRAM_ECC</span></code></td>
<td>0x00000200</td>
<td>Indicates if the <code class="docutils literal notranslate"><span class="pre">sram-ecc</span></code>
target feature is
enabled for all code
contained in the code object.
If the processor
does not support the
<code class="docutils literal notranslate"><span class="pre">sram-ecc</span></code> target
feature then must
be 0.
See
<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
</tr>
</tbody>
</table>
<table border="1" class="last docutils" id="amdgpu-ef-amdgpu-mach-table">
<caption><span class="caption-text">AMDGPU <code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code> Values</span><a class="headerlink" href="#amdgpu-ef-amdgpu-mach-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="45%" />
<col width="14%" />
<col width="41%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Value</th>
<th class="head">Description (see
<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>)</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_NONE</span></code></td>
<td>0x000</td>
<td><em>not specified</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_R600</span></code></td>
<td>0x001</td>
<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_R630</span></code></td>
<td>0x002</td>
<td><code class="docutils literal notranslate"><span class="pre">r630</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RS880</span></code></td>
<td>0x003</td>
<td><code class="docutils literal notranslate"><span class="pre">rs880</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV670</span></code></td>
<td>0x004</td>
<td><code class="docutils literal notranslate"><span class="pre">rv670</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV710</span></code></td>
<td>0x005</td>
<td><code class="docutils literal notranslate"><span class="pre">rv710</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV730</span></code></td>
<td>0x006</td>
<td><code class="docutils literal notranslate"><span class="pre">rv730</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV770</span></code></td>
<td>0x007</td>
<td><code class="docutils literal notranslate"><span class="pre">rv770</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CEDAR</span></code></td>
<td>0x008</td>
<td><code class="docutils literal notranslate"><span class="pre">cedar</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CYPRESS</span></code></td>
<td>0x009</td>
<td><code class="docutils literal notranslate"><span class="pre">cypress</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_JUNIPER</span></code></td>
<td>0x00a</td>
<td><code class="docutils literal notranslate"><span class="pre">juniper</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_REDWOOD</span></code></td>
<td>0x00b</td>
<td><code class="docutils literal notranslate"><span class="pre">redwood</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_SUMO</span></code></td>
<td>0x00c</td>
<td><code class="docutils literal notranslate"><span class="pre">sumo</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_BARTS</span></code></td>
<td>0x00d</td>
<td><code class="docutils literal notranslate"><span class="pre">barts</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CAICOS</span></code></td>
<td>0x00e</td>
<td><code class="docutils literal notranslate"><span class="pre">caicos</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CAYMAN</span></code></td>
<td>0x00f</td>
<td><code class="docutils literal notranslate"><span class="pre">cayman</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_TURKS</span></code></td>
<td>0x010</td>
<td><code class="docutils literal notranslate"><span class="pre">turks</span></code></td>
</tr>
<tr class="row-odd"><td><em>reserved</em></td>
<td>0x011 -
0x01f</td>
<td>Reserved for <code class="docutils literal notranslate"><span class="pre">r600</span></code>
architecture processors.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX600</span></code></td>
<td>0x020</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx600</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX601</span></code></td>
<td>0x021</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx601</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX700</span></code></td>
<td>0x022</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx700</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX701</span></code></td>
<td>0x023</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx701</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX702</span></code></td>
<td>0x024</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx702</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX703</span></code></td>
<td>0x025</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx703</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX704</span></code></td>
<td>0x026</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx704</span></code></td>
</tr>
<tr class="row-odd"><td><em>reserved</em></td>
<td>0x027</td>
<td>Reserved.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX801</span></code></td>
<td>0x028</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx801</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX802</span></code></td>
<td>0x029</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx802</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX803</span></code></td>
<td>0x02a</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx803</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX810</span></code></td>
<td>0x02b</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx810</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX900</span></code></td>
<td>0x02c</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx900</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX902</span></code></td>
<td>0x02d</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx902</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX904</span></code></td>
<td>0x02e</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx904</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX906</span></code></td>
<td>0x02f</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx906</span></code></td>
</tr>
<tr class="row-even"><td><em>reserved</em></td>
<td>0x030</td>
<td>Reserved.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX909</span></code></td>
<td>0x031</td>
<td><code class="docutils literal notranslate"><span class="pre">gfx909</span></code></td>
</tr>
</tbody>
</table>
</dd>
</dl>
</div>
<div class="section" id="sections">
<h3><a class="toc-backref" href="#id57">Sections</a><a class="headerlink" href="#sections" title="Permalink to this headline">¶</a></h3>
<p>An AMDGPU target ELF code object has the standard ELF sections which include:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-sections-table">
<caption><span class="caption-text">AMDGPU ELF Sections</span><a class="headerlink" href="#amdgpu-elf-sections-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="27%" />
<col width="24%" />
<col width="49%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Type</th>
<th class="head">Attributes</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.bss</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_NOBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.data</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.debug_</span></code><em>*</em></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.dynamic</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_DYNAMIC</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.dynstr</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.dynsym</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.got</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.hash</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_HASH</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.note</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_NOTE</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_RELA</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_RELA</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.shstrtab</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_STRTAB</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.strtab</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_STRTAB</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.symtab</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_SYMTAB</span></code></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.text</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_EXECINSTR</span></code></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>These sections have their standard meanings (see <a class="reference internal" href="#elf" id="id19">[ELF]</a>) and are only generated
if needed.</p>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">.debug</span></code><em>*</em></dt>
<dd>The standard DWARF sections. See <a class="reference internal" href="#amdgpu-dwarf"><span class="std std-ref">DWARF</span></a> for information on the
DWARF produced by the AMDGPU backend.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">.dynamic</span></code>, <code class="docutils literal notranslate"><span class="pre">.dynstr</span></code>, <code class="docutils literal notranslate"><span class="pre">.dynsym</span></code>, <code class="docutils literal notranslate"><span class="pre">.hash</span></code></dt>
<dd>The standard sections used by a dynamic loader.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">.note</span></code></dt>
<dd>See <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a> for the note records supported by the AMDGPU
backend.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em>, <code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code></dt>
<dd><p class="first">For relocatable code objects, <em>name</em> is the name of the section that the
relocation records apply. For example, <code class="docutils literal notranslate"><span class="pre">.rela.text</span></code> is the section name for
relocation records associated with the <code class="docutils literal notranslate"><span class="pre">.text</span></code> section.</p>
<p>For linked shared code objects, <code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code> contains all the relocation
records from each of the relocatable code object’s <code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em> sections.</p>
<p class="last">See <a class="reference internal" href="#amdgpu-relocation-records"><span class="std std-ref">Relocation Records</span></a> for the relocation records supported by
the AMDGPU backend.</p>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">.text</span></code></dt>
<dd>The executable machine code for the kernels and functions they call. Generated
as position independent code. See <a class="reference internal" href="#amdgpu-code-conventions"><span class="std std-ref">Code Conventions</span></a> for
information on conventions used in the isa generation.</dd>
</dl>
</div>
<div class="section" id="note-records">
<span id="amdgpu-note-records"></span><h3><a class="toc-backref" href="#id58">Note Records</a><a class="headerlink" href="#note-records" title="Permalink to this headline">¶</a></h3>
<p>As required by <code class="docutils literal notranslate"><span class="pre">ELFCLASS32</span></code> and <code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code>, minimal zero byte padding must
be generated after the <code class="docutils literal notranslate"><span class="pre">name</span></code> field to ensure the <code class="docutils literal notranslate"><span class="pre">desc</span></code> field is 4 byte
aligned. In addition, minimal zero byte padding must be generated to ensure the
<code class="docutils literal notranslate"><span class="pre">desc</span></code> field size is a multiple of 4 bytes. The <code class="docutils literal notranslate"><span class="pre">sh_addralign</span></code> field of the
<code class="docutils literal notranslate"><span class="pre">.note</span></code> section must be at least 4 to indicate at least 8 byte alignment.</p>
<div class="section" id="code-object-v2-note-records-mattr-code-object-v3">
<span id="amdgpu-note-records-v2"></span><h4><a class="toc-backref" href="#id59">Code Object V2 Note Records (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-note-records-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
<p>The AMDGPU backend code object uses the following ELF note record in the
<code class="docutils literal notranslate"><span class="pre">.note</span></code> section.</p>
<p>Additional note records can be present.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table-v2">
<caption><span class="caption-text">AMDGPU Code Object V2 ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="7%" />
<col width="41%" />
<col width="52%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Type</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“AMD”</td>
<td><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
<td><metadata null terminated string></td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table-v2">
<caption><span class="caption-text">AMDGPU Code Object V2 ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="86%" />
<col width="14%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><em>reserved</em></td>
<td>0-9</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
<td>10</td>
</tr>
<tr class="row-even"><td><em>reserved</em></td>
<td>11</td>
</tr>
</tbody>
</table>
</div></blockquote>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></dt>
<dd>Specifies extensible metadata associated with the code objects executed on HSA
<a class="reference internal" href="#hsa" id="id20">[HSA]</a> compatible runtimes such as AMD’s ROCm <a class="reference internal" href="#amd-rocm" id="id21">[AMD-ROCm]</a>. It is required when
the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v2"><span class="std std-ref">Code Object V2 Metadata (-mattr=-code-object-v3)</span></a> for the syntax of the code
object metadata string.</dd>
</dl>
</div>
<div class="section" id="code-object-v3-note-records-mattr-code-object-v3">
<span id="amdgpu-note-records-v3"></span><h4><a class="toc-backref" href="#id60">Code Object V3 Note Records (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-note-records-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
<p>The AMDGPU backend code object uses the following ELF note record in the
<code class="docutils literal notranslate"><span class="pre">.note</span></code> section.</p>
<p>Additional note records can be present.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table-v3">
<caption><span class="caption-text">AMDGPU Code Object V3 ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table-v3" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="11%" />
<col width="39%" />
<col width="50%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Type</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“AMDGPU”</td>
<td><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></td>
<td>Metadata in Message Pack <a class="reference internal" href="#msgpack" id="id22">[MsgPack]</a>
binary format.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table-v3">
<caption><span class="caption-text">AMDGPU Code Object V3 ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table-v3" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="86%" />
<col width="14%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><em>reserved</em></td>
<td>0-31</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></td>
<td>32</td>
</tr>
</tbody>
</table>
</div></blockquote>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></dt>
<dd>Specifies extensible metadata associated with an AMDGPU code
object. It is encoded as a map in the Message Pack <a class="reference internal" href="#msgpack" id="id23">[MsgPack]</a> binary
data format. See <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a> for the
map keys defined for the <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS.</dd>
</dl>
</div>
</div>
<div class="section" id="symbols">
<span id="amdgpu-symbols"></span><h3><a class="toc-backref" href="#id61">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
<p>Symbols include the following:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-symbols-table">
<caption><span class="caption-text">AMDGPU ELF Symbols</span><a class="headerlink" href="#amdgpu-elf-symbols-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="32%" />
<col width="21%" />
<col width="20%" />
<col width="27%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Name</th>
<th class="head">Type</th>
<th class="head">Section</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><em>link-name</em></td>
<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">.data</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">.bss</span></code></li>
</ul>
</td>
<td>Global variable</td>
</tr>
<tr class="row-odd"><td><em>link-name</em><code class="docutils literal notranslate"><span class="pre">.kd</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></li>
</ul>
</td>
<td>Kernel descriptor</td>
</tr>
<tr class="row-even"><td><em>link-name</em></td>
<td><code class="docutils literal notranslate"><span class="pre">STT_FUNC</span></code></td>
<td><ul class="first last simple">
<li><code class="docutils literal notranslate"><span class="pre">.text</span></code></li>
</ul>
</td>
<td>Kernel entry point</td>
</tr>
</tbody>
</table>
</div></blockquote>
<dl class="docutils">
<dt>Global variable</dt>
<dd><p class="first">Global variables both used and defined by the compilation unit.</p>
<p>If the symbol is defined in the compilation unit then it is allocated in the
appropriate section according to if it has initialized data or is readonly.</p>
<p>If the symbol is external then its section is <code class="docutils literal notranslate"><span class="pre">STN_UNDEF</span></code> and the loader
will resolve relocations using the definition provided by another code object
or explicitly defined by the runtime.</p>
<p class="last">All global symbols, whether defined in the compilation unit or external, are
accessed by the machine code indirectly through a GOT table entry. This
allows them to be preemptable. The GOT table is only supported when the target
triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
</dd>
<dt>Kernel descriptor</dt>
<dd>Every HSA kernel has an associated kernel descriptor. It is the address of the
kernel descriptor that is used in the AQL dispatch packet used to invoke the
kernel, not the kernel entry point. The layout of the HSA kernel descriptor is
defined in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.</dd>
<dt>Kernel entry point</dt>
<dd>Every HSA kernel also has a symbol for its machine code entry point.</dd>
</dl>
</div>
<div class="section" id="relocation-records">
<span id="amdgpu-relocation-records"></span><h3><a class="toc-backref" href="#id62">Relocation Records</a><a class="headerlink" href="#relocation-records" title="Permalink to this headline">¶</a></h3>
<p>AMDGPU backend generates <code class="docutils literal notranslate"><span class="pre">Elf64_Rela</span></code> relocation records. Supported
relocatable fields are:</p>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">word32</span></code></dt>
<dd>This specifies a 32-bit field occupying 4 bytes with arbitrary byte
alignment. These values use the same byte order as other word values in the
AMD GPU architecture.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">word64</span></code></dt>
<dd>This specifies a 64-bit field occupying 8 bytes with arbitrary byte
alignment. These values use the same byte order as other word values in the
AMD GPU architecture.</dd>
</dl>
<p>Following notations are used for specifying relocation calculations:</p>
<dl class="docutils">
<dt><strong>A</strong></dt>
<dd>Represents the addend used to compute the value of the relocatable field.</dd>
<dt><strong>G</strong></dt>
<dd>Represents the offset into the global offset table at which the relocation
entry’s symbol will reside during execution.</dd>
<dt><strong>GOT</strong></dt>
<dd>Represents the address of the global offset table.</dd>
<dt><strong>P</strong></dt>
<dd>Represents the place (section offset for <code class="docutils literal notranslate"><span class="pre">et_rel</span></code> or address for <code class="docutils literal notranslate"><span class="pre">et_dyn</span></code>)
of the storage unit being relocated (computed using <code class="docutils literal notranslate"><span class="pre">r_offset</span></code>).</dd>
<dt><strong>S</strong></dt>
<dd>Represents the value of the symbol whose index resides in the relocation
entry. Relocations not using this must specify a symbol index of <code class="docutils literal notranslate"><span class="pre">STN_UNDEF</span></code>.</dd>
<dt><strong>B</strong></dt>
<dd>Represents the base address of a loaded executable or shared object which is
the difference between the ELF address and the actual load address. Relocations
using this are only valid in executable or shared objects.</dd>
</dl>
<p>The following relocation types are supported:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-elf-relocation-records-table">
<caption><span class="caption-text">AMDGPU ELF Relocation Records</span><a class="headerlink" href="#amdgpu-elf-relocation-records-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="33%" />
<col width="9%" />
<col width="6%" />
<col width="13%" />
<col width="38%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Relocation Type</th>
<th class="head">Kind</th>
<th class="head">Value</th>
<th class="head">Field</th>
<th class="head">Calculation</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_NONE</span></code></td>
<td> </td>
<td>0</td>
<td><em>none</em></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_LO</span></code></td>
<td>Static,
Dynamic</td>
<td>1</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>(S + A) & 0xFFFFFFFF</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_HI</span></code></td>
<td>Static,
Dynamic</td>
<td>2</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>(S + A) >> 32</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS64</span></code></td>
<td>Static,
Dynamic</td>
<td>3</td>
<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
<td>S + A</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32</span></code></td>
<td>Static</td>
<td>4</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>S + A - P</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL64</span></code></td>
<td>Static</td>
<td>5</td>
<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
<td>S + A - P</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32</span></code></td>
<td>Static,
Dynamic</td>
<td>6</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>S + A</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL</span></code></td>
<td>Static</td>
<td>7</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>G + GOT + A - P</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL32_LO</span></code></td>
<td>Static</td>
<td>8</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>(G + GOT + A - P) & 0xFFFFFFFF</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL32_HI</span></code></td>
<td>Static</td>
<td>9</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>(G + GOT + A - P) >> 32</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32_LO</span></code></td>
<td>Static</td>
<td>10</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>(S + A - P) & 0xFFFFFFFF</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32_HI</span></code></td>
<td>Static</td>
<td>11</td>
<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
<td>(S + A - P) >> 32</td>
</tr>
<tr class="row-even"><td><em>reserved</em></td>
<td> </td>
<td>12</td>
<td> </td>
<td> </td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_RELATIVE64</span></code></td>
<td>Dynamic</td>
<td>13</td>
<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
<td>B + A</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_LO</span></code> and <code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_HI</span></code> are only supported by
the <code class="docutils literal notranslate"><span class="pre">mesa3d</span></code> OS, which does not support <code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS64</span></code>.</p>
<p>There is no current OS loader support for 32 bit programs and so
<code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32</span></code> is not used.</p>
</div>
<div class="section" id="dwarf">
<span id="amdgpu-dwarf"></span><h3><a class="toc-backref" href="#id63">DWARF</a><a class="headerlink" href="#dwarf" title="Permalink to this headline">¶</a></h3>
<p>Standard DWARF <a class="reference internal" href="#id44" id="id24">[DWARF]</a> Version 5 sections can be generated. These contain
information that maps the code object executable code and data to the source
language constructs. It can be used by tools such as debuggers and profilers.</p>
<div class="section" id="address-space-mapping">
<h4><a class="toc-backref" href="#id64">Address Space Mapping</a><a class="headerlink" href="#address-space-mapping" title="Permalink to this headline">¶</a></h4>
<p>The following address space mapping is used:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-dwarf-address-space-mapping-table">
<caption><span class="caption-text">AMDGPU DWARF Address Space Mapping</span><a class="headerlink" href="#amdgpu-dwarf-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="53%" />
<col width="47%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">DWARF Address Space</th>
<th class="head">Memory Space</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>1</td>
<td>Private (Scratch)</td>
</tr>
<tr class="row-odd"><td>2</td>
<td>Local (group/LDS)</td>
</tr>
<tr class="row-even"><td><em>omitted</em></td>
<td>Global</td>
</tr>
<tr class="row-odd"><td><em>omitted</em></td>
<td>Constant</td>
</tr>
<tr class="row-even"><td><em>omitted</em></td>
<td>Generic (Flat)</td>
</tr>
<tr class="row-odd"><td><em>not supported</em></td>
<td>Region (GDS)</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>See <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a> for information on the memory space terminology
used in the table.</p>
<p>An <code class="docutils literal notranslate"><span class="pre">address_class</span></code> attribute is generated on pointer type DIEs to specify the
DWARF address space of the value of the pointer when it is in the <em>private</em> or
<em>local</em> address space. Otherwise the attribute is omitted.</p>
<p>An <code class="docutils literal notranslate"><span class="pre">XDEREF</span></code> operation is generated in location list expressions for variables
that are allocated in the <em>private</em> and <em>local</em> address space. Otherwise no
<code class="docutils literal notranslate"><span class="pre">XDREF</span></code> is omitted.</p>
</div>
<div class="section" id="register-mapping">
<h4><a class="toc-backref" href="#id65">Register Mapping</a><a class="headerlink" href="#register-mapping" title="Permalink to this headline">¶</a></h4>
<p><em>This section is WIP.</em></p>
</div>
<div class="section" id="source-text">
<h4><a class="toc-backref" href="#id66">Source Text</a><a class="headerlink" href="#source-text" title="Permalink to this headline">¶</a></h4>
<p>Source text for online-compiled programs (e.g. those compiled by the OpenCL
runtime) may be embedded into the DWARF v5 line table using the <code class="docutils literal notranslate"><span class="pre">clang</span>
<span class="pre">-gembed-source</span></code> option, described in table <a class="reference internal" href="#amdgpu-debug-options"><span class="std std-ref">AMDGPU Debug Options</span></a>.</p>
<p>For example:</p>
<dl class="docutils">
<dt><code class="docutils literal notranslate"><span class="pre">-gembed-source</span></code></dt>
<dd>Enable the embedded source DWARF v5 extension.</dd>
<dt><code class="docutils literal notranslate"><span class="pre">-gno-embed-source</span></code></dt>
<dd><p class="first">Disable the embedded source DWARF v5 extension.</p>
<table border="1" class="last docutils" id="amdgpu-debug-options">
<caption><span class="caption-text">AMDGPU Debug Options</span><a class="headerlink" href="#amdgpu-debug-options" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="29%" />
<col width="71%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Debug Flag</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>-g[no-]embed-source</td>
<td>Enable/disable embedding source text in DWARF
debug sections. Useful for environments where
source cannot be written to disk, such as
when performing online compilation.</td>
</tr>
</tbody>
</table>
</dd>
</dl>
<p>This option enables one extended content types in the DWARF v5 Line Number
Program Header, which is used to encode embedded source.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-dwarf-extended-content-types">
<caption><span class="caption-text">AMDGPU DWARF Line Number Program Header Extended Content Types</span><a class="headerlink" href="#amdgpu-dwarf-extended-content-types" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="56%" />
<col width="44%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Content Type</th>
<th class="head">Form</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">DW_LNCT_LLVM_source</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">DW_FORM_line_strp</span></code></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>The source field will contain the UTF-8 encoded, null-terminated source text
with <code class="docutils literal notranslate"><span class="pre">'\n'</span></code> line endings. When the source field is present, consumers can use
the embedded source instead of attempting to discover the source on disk. When
the source field is absent, consumers can access the file to get the source
text.</p>
<p>The above content type appears in the <code class="docutils literal notranslate"><span class="pre">file_name_entry_format</span></code> field of the
line table prologue, and its corresponding value appear in the <code class="docutils literal notranslate"><span class="pre">file_names</span></code>
field. The current encoding of the content type is documented in table
<a class="reference internal" href="#amdgpu-dwarf-extended-content-types-encoding"><span class="std std-ref">AMDGPU DWARF Line Number Program Header Extended Content Types Encoding</span></a></p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-dwarf-extended-content-types-encoding">
<caption><span class="caption-text">AMDGPU DWARF Line Number Program Header Extended Content Types Encoding</span><a class="headerlink" href="#amdgpu-dwarf-extended-content-types-encoding" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="58%" />
<col width="42%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Content Type</th>
<th class="head">Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">DW_LNCT_LLVM_source</span></code></td>
<td>0x2001</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
</div>
<div class="section" id="code-conventions">
<span id="amdgpu-code-conventions"></span><h2><a class="toc-backref" href="#id67">Code Conventions</a><a class="headerlink" href="#code-conventions" title="Permalink to this headline">¶</a></h2>
<p>This section provides code conventions used for each supported target triple OS
(see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
<div class="section" id="amdhsa">
<h3><a class="toc-backref" href="#id68">AMDHSA</a><a class="headerlink" href="#amdhsa" title="Permalink to this headline">¶</a></h3>
<p>This section provides code conventions used when the target triple OS is
<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
<div class="section" id="code-object-target-identification">
<span id="amdgpu-amdhsa-code-object-target-identification"></span><h4><a class="toc-backref" href="#id69">Code Object Target Identification</a><a class="headerlink" href="#code-object-target-identification" title="Permalink to this headline">¶</a></h4>
<p>The AMDHSA OS uses the following syntax to specify the code object
target as a single string:</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre"><Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target</span> <span class="pre">Features></span></code></div></blockquote>
<p>Where:</p>
<blockquote>
<div><ul class="simple">
<li><code class="docutils literal notranslate"><span class="pre"><Architecture></span></code>, <code class="docutils literal notranslate"><span class="pre"><Vendor></span></code>, <code class="docutils literal notranslate"><span class="pre"><OS></span></code> and <code class="docutils literal notranslate"><span class="pre"><Environment></span></code>
are the same as the <em>Target Triple</em> (see
<a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</li>
<li><code class="docutils literal notranslate"><span class="pre"><Processor></span></code> is the same as the <em>Processor</em> (see
<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>).</li>
<li><code class="docutils literal notranslate"><span class="pre"><Target</span> <span class="pre">Features></span></code> is a list of the enabled <em>Target Features</em>
(see <a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>), each prefixed by a plus, that
apply to <em>Processor</em>. The list must be in the same order as listed
in the table <a class="reference internal" href="#amdgpu-target-feature-table"><span class="std std-ref">AMDGPU Target Features</span></a>. Note that <em>Target
Features</em> must be included in the list if they are enabled even if
that is the default for <em>Processor</em>.</li>
</ul>
</div></blockquote>
<p>For example:</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre">"amdgcn-amd-amdhsa--gfx902+xnack"</span></code></div></blockquote>
</div>
<div class="section" id="code-object-metadata">
<span id="amdgpu-amdhsa-code-object-metadata"></span><h4><a class="toc-backref" href="#id70">Code Object Metadata</a><a class="headerlink" href="#code-object-metadata" title="Permalink to this headline">¶</a></h4>
<p>The code object metadata specifies extensible metadata associated with the code
objects executed on HSA <a class="reference internal" href="#hsa" id="id25">[HSA]</a> compatible runtimes such as AMD’s ROCm
<a class="reference internal" href="#amd-rocm" id="id26">[AMD-ROCm]</a>. It is specified in a note record (see <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a>)
and is required when the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see
<a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). It must contain the minimum information
necessary to support the ROCM kernel queries. For example, the segment sizes
needed in a dispatch packet. In addition, a high level language runtime may
require other information to be included. For example, the AMD OpenCL runtime
records kernel argument information.</p>
<div class="section" id="code-object-v2-metadata-mattr-code-object-v3">
<span id="amdgpu-amdhsa-code-object-metadata-v2"></span><h5><a class="toc-backref" href="#id71">Code Object V2 Metadata (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-metadata-mattr-code-object-v3" title="Permalink to this headline">¶</a></h5>
<p>Code object V2 metadata is specified by the <code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_METADATA</span></code> note
record (see <a class="reference internal" href="#amdgpu-note-records-v2"><span class="std std-ref">Code Object V2 Note Records (-mattr=-code-object-v3)</span></a>).</p>
<p>The metadata is specified as a YAML formatted string (see <a class="reference internal" href="#yaml" id="id27">[YAML]</a> and
<a class="reference internal" href="YamlIO.html"><span class="doc">YAML I/O</span></a>).</p>
<p>The metadata is represented as a single YAML document comprised of the mapping
defined in table <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Metadata Map</span></a> and
referenced tables.</p>
<p>For boolean values, the string values of <code class="docutils literal notranslate"><span class="pre">false</span></code> and <code class="docutils literal notranslate"><span class="pre">true</span></code> are used for
false and true respectively.</p>
<p>Additional information can be added to the mappings. To avoid conflicts, any
non-AMD key names should be prefixed by “<em>vendor-name</em>.”.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-map-table-v2">
<caption><span class="caption-text">AMDHSA Code Object V2 Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="11%" />
<col width="15%" />
<col width="10%" />
<col width="65%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“Version”</td>
<td>sequence of
2 integers</td>
<td>Required</td>
<td><ul class="first last simple">
<li>The first integer is the major
version. Currently 1.</li>
<li>The second integer is the minor
version. Currently 0.</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>“Printf”</td>
<td>sequence of
strings</td>
<td> </td>
<td><p class="first">Each string is encoded information
about a printf function call. The
encoded information is organized as
fields separated by colon (‘:’):</p>
<p><code class="docutils literal notranslate"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
<p>where:</p>
<dl class="last docutils">
<dt><code class="docutils literal notranslate"><span class="pre">ID</span></code></dt>
<dd>A 32 bit integer as a unique id for
each printf function call</dd>
<dt><code class="docutils literal notranslate"><span class="pre">N</span></code></dt>
<dd>A 32 bit integer equal to the number
of arguments of printf function call
minus 1</dd>
<dt><code class="docutils literal notranslate"><span class="pre">S[i]</span></code> (where i = 0, 1, … , N-1)</dt>
<dd>32 bit integers for the size in bytes
of the i-th FormatString argument of
the printf function call</dd>
<dt>FormatString</dt>
<dd>The format string passed to the
printf function call.</dd>
</dl>
</td>
</tr>
<tr class="row-even"><td>“Kernels”</td>
<td>sequence of
mapping</td>
<td>Required</td>
<td>Sequence of the mappings for each
kernel in the code object. See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Metadata Map</span></a>
for the definition of the mapping.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2">
<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="15%" />
<col width="12%" />
<col width="8%" />
<col width="66%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“Name”</td>
<td>string</td>
<td>Required</td>
<td>Source name of the kernel.</td>
</tr>
<tr class="row-odd"><td>“SymbolName”</td>
<td>string</td>
<td>Required</td>
<td>Name of the kernel
descriptor ELF symbol.</td>
</tr>
<tr class="row-even"><td>“Language”</td>
<td>string</td>
<td> </td>
<td><p class="first">Source language of the kernel.
Values include:</p>
<ul class="last simple">
<li>“OpenCL C”</li>
<li>“OpenCL C++”</li>
<li>“HCC”</li>
<li>“OpenMP”</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>“LanguageVersion”</td>
<td>sequence of
2 integers</td>
<td> </td>
<td><ul class="first last simple">
<li>The first integer is the major
version.</li>
<li>The second integer is the
minor version.</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“Attrs”</td>
<td>mapping</td>
<td> </td>
<td>Mapping of kernel attributes.
See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Attribute Metadata Map</span></a>
for the mapping definition.</td>
</tr>
<tr class="row-odd"><td>“Args”</td>
<td>sequence of
mapping</td>
<td> </td>
<td>Sequence of mappings of the
kernel arguments. See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Argument Metadata Map</span></a>
for the definition of the mapping.</td>
</tr>
<tr class="row-even"><td>“CodeProps”</td>
<td>mapping</td>
<td> </td>
<td>Mapping of properties related to
the kernel code. See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Code Properties Metadata Map</span></a>
for the mapping definition.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2">
<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Attribute Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="26%" />
<col width="19%" />
<col width="13%" />
<col width="42%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“ReqdWorkGroupSize”</td>
<td>sequence of
3 integers</td>
<td> </td>
<td><p class="first">If not 0, 0, 0 then all values
must be >=1 and the dispatch
work-group size X, Y, Z must
correspond to the specified
values. Defaults to 0, 0, 0.</p>
<p class="last">Corresponds to the OpenCL
<code class="docutils literal notranslate"><span class="pre">reqd_work_group_size</span></code>
attribute.</p>
</td>
</tr>
<tr class="row-odd"><td>“WorkGroupSizeHint”</td>
<td>sequence of
3 integers</td>
<td> </td>
<td><p class="first">The dispatch work-group size
X, Y, Z is likely to be the
specified values.</p>
<p class="last">Corresponds to the OpenCL
<code class="docutils literal notranslate"><span class="pre">work_group_size_hint</span></code>
attribute.</p>
</td>
</tr>
<tr class="row-even"><td>“VecTypeHint”</td>
<td>string</td>
<td> </td>
<td><p class="first">The name of a scalar or vector
type.</p>
<p class="last">Corresponds to the OpenCL
<code class="docutils literal notranslate"><span class="pre">vec_type_hint</span></code> attribute.</p>
</td>
</tr>
<tr class="row-odd"><td>“RuntimeHandle”</td>
<td>string</td>
<td> </td>
<td>The external symbol name
associated with a kernel.
OpenCL runtime allocates a
global buffer for the symbol
and saves the kernel’s address
to it, which is used for
device side enqueueing. Only
available for device side
enqueued kernels.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2">
<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Argument Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="22%" />
<col width="18%" />
<col width="12%" />
<col width="49%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“Name”</td>
<td>string</td>
<td> </td>
<td>Kernel argument name.</td>
</tr>
<tr class="row-odd"><td>“TypeName”</td>
<td>string</td>
<td> </td>
<td>Kernel argument type name.</td>
</tr>
<tr class="row-even"><td>“Size”</td>
<td>integer</td>
<td>Required</td>
<td>Kernel argument size in bytes.</td>
</tr>
<tr class="row-odd"><td>“Align”</td>
<td>integer</td>
<td>Required</td>
<td>Kernel argument alignment in
bytes. Must be a power of two.</td>
</tr>
<tr class="row-even"><td>“ValueKind”</td>
<td>string</td>
<td>Required</td>
<td><p class="first">Kernel argument kind that
specifies how to set up the
corresponding argument.
Values include:</p>
<dl class="last docutils">
<dt>“ByValue”</dt>
<dd>The argument is copied
directly into the kernarg.</dd>
<dt>“GlobalBuffer”</dt>
<dd>A global address space pointer
to the buffer data is passed
in the kernarg.</dd>
<dt>“DynamicSharedPointer”</dt>
<dd>A group address space pointer
to dynamically allocated LDS
is passed in the kernarg.</dd>
<dt>“Sampler”</dt>
<dd>A global address space
pointer to a S# is passed in
the kernarg.</dd>
<dt>“Image”</dt>
<dd>A global address space
pointer to a T# is passed in
the kernarg.</dd>
<dt>“Pipe”</dt>
<dd>A global address space pointer
to an OpenCL pipe is passed in
the kernarg.</dd>
<dt>“Queue”</dt>
<dd>A global address space pointer
to an OpenCL device enqueue
queue is passed in the
kernarg.</dd>
<dt>“HiddenGlobalOffsetX”</dt>
<dd>The OpenCL grid dispatch
global offset for the X
dimension is passed in the
kernarg.</dd>
<dt>“HiddenGlobalOffsetY”</dt>
<dd>The OpenCL grid dispatch
global offset for the Y
dimension is passed in the
kernarg.</dd>
<dt>“HiddenGlobalOffsetZ”</dt>
<dd>The OpenCL grid dispatch
global offset for the Z
dimension is passed in the
kernarg.</dd>
<dt>“HiddenNone”</dt>
<dd>An argument that is not used
by the kernel. Space needs to
be left for it, but it does
not need to be set up.</dd>
<dt>“HiddenPrintfBuffer”</dt>
<dd>A global address space pointer
to the runtime printf buffer
is passed in kernarg.</dd>
<dt>“HiddenDefaultQueue”</dt>
<dd>A global address space pointer
to the OpenCL device enqueue
queue that should be used by
the kernel by default is
passed in the kernarg.</dd>
<dt>“HiddenCompletionAction”</dt>
<dd>A global address space pointer
to help link enqueued kernels into
the ancestor tree for determining
when the parent kernel has finished.</dd>
</dl>
</td>
</tr>
<tr class="row-odd"><td>“ValueType”</td>
<td>string</td>
<td>Required</td>
<td><p class="first">Kernel argument value type. Only
present if “ValueKind” is
“ByValue”. For vector data
types, the value is for the
element type. Values include:</p>
<ul class="last simple">
<li>“Struct”</li>
<li>“I8”</li>
<li>“U8”</li>
<li>“I16”</li>
<li>“U16”</li>
<li>“F16”</li>
<li>“I32”</li>
<li>“U32”</li>
<li>“F32”</li>
<li>“I64”</li>
<li>“U64”</li>
<li>“F64”</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“PointeeAlign”</td>
<td>integer</td>
<td> </td>
<td>Alignment in bytes of pointee
type for pointer type kernel
argument. Must be a power
of 2. Only present if
“ValueKind” is
“DynamicSharedPointer”.</td>
</tr>
<tr class="row-odd"><td>“AddrSpaceQual”</td>
<td>string</td>
<td> </td>
<td><p class="first">Kernel argument address space
qualifier. Only present if
“ValueKind” is “GlobalBuffer” or
“DynamicSharedPointer”. Values
are:</p>
<ul class="last simple">
<li>“Private”</li>
<li>“Global”</li>
<li>“Constant”</li>
<li>“Local”</li>
<li>“Generic”</li>
<li>“Region”</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“AccQual”</td>
<td>string</td>
<td> </td>
<td><p class="first">Kernel argument access
qualifier. Only present if
“ValueKind” is “Image” or
“Pipe”. Values
are:</p>
<ul class="last simple">
<li>“ReadOnly”</li>
<li>“WriteOnly”</li>
<li>“ReadWrite”</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>“ActualAccQual”</td>
<td>string</td>
<td> </td>
<td><p class="first">The actual memory accesses
performed by the kernel on the
kernel argument. Only present if
“ValueKind” is “GlobalBuffer”,
“Image”, or “Pipe”. This may be
more restrictive than indicated
by “AccQual” to reflect what the
kernel actual does. If not
present then the runtime must
assume what is implied by
“AccQual” and “IsConst”. Values
are:</p>
<ul class="last simple">
<li>“ReadOnly”</li>
<li>“WriteOnly”</li>
<li>“ReadWrite”</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“IsConst”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is const qualified. Only present
if “ValueKind” is
“GlobalBuffer”.</td>
</tr>
<tr class="row-odd"><td>“IsRestrict”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is restrict qualified. Only
present if “ValueKind” is
“GlobalBuffer”.</td>
</tr>
<tr class="row-even"><td>“IsVolatile”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is volatile qualified. Only
present if “ValueKind” is
“GlobalBuffer”.</td>
</tr>
<tr class="row-odd"><td>“IsPipe”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is pipe qualified. Only present
if “ValueKind” is “Pipe”.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2">
<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Code Properties Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="39%" />
<col width="19%" />
<col width="13%" />
<col width="29%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“KernargSegmentSize”</td>
<td>integer</td>
<td>Required</td>
<td>The size in bytes of
the kernarg segment
that holds the values
of the arguments to
the kernel.</td>
</tr>
<tr class="row-odd"><td>“GroupSegmentFixedSize”</td>
<td>integer</td>
<td>Required</td>
<td>The amount of group
segment memory
required by a
work-group in
bytes. This does not
include any
dynamically allocated
group segment memory
that may be added
when the kernel is
dispatched.</td>
</tr>
<tr class="row-even"><td>“PrivateSegmentFixedSize”</td>
<td>integer</td>
<td>Required</td>
<td>The amount of fixed
private address space
memory required for a
work-item in
bytes. If the kernel
uses a dynamic call
stack then additional
space must be added
to this value for the
call stack.</td>
</tr>
<tr class="row-odd"><td>“KernargSegmentAlign”</td>
<td>integer</td>
<td>Required</td>
<td>The maximum byte
alignment of
arguments in the
kernarg segment. Must
be a power of 2.</td>
</tr>
<tr class="row-even"><td>“WavefrontSize”</td>
<td>integer</td>
<td>Required</td>
<td>Wavefront size. Must
be a power of 2.</td>
</tr>
<tr class="row-odd"><td>“NumSGPRs”</td>
<td>integer</td>
<td>Required</td>
<td>Number of scalar
registers used by a
wavefront for
GFX6-GFX9. This
includes the special
SGPRs for VCC, Flat
Scratch (GFX7-GFX9)
and XNACK (for
GFX8-GFX9). It does
not include the 16
SGPR added if a trap
handler is
enabled. It is not
rounded up to the
allocation
granularity.</td>
</tr>
<tr class="row-even"><td>“NumVGPRs”</td>
<td>integer</td>
<td>Required</td>
<td>Number of vector
registers used by
each work-item for
GFX6-GFX9</td>
</tr>
<tr class="row-odd"><td>“MaxFlatWorkGroupSize”</td>
<td>integer</td>
<td>Required</td>
<td>Maximum flat
work-group size
supported by the
kernel in work-items.
Must be >=1 and
consistent with
ReqdWorkGroupSize if
not 0, 0, 0.</td>
</tr>
<tr class="row-even"><td>“NumSpilledSGPRs”</td>
<td>integer</td>
<td> </td>
<td>Number of stores from
a scalar register to
a register allocator
created spill
location.</td>
</tr>
<tr class="row-odd"><td>“NumSpilledVGPRs”</td>
<td>integer</td>
<td> </td>
<td>Number of stores from
a vector register to
a register allocator
created spill
location.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="code-object-v3-metadata-mattr-code-object-v3">
<span id="amdgpu-amdhsa-code-object-metadata-v3"></span><h5><a class="toc-backref" href="#id72">Code Object V3 Metadata (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-metadata-mattr-code-object-v3" title="Permalink to this headline">¶</a></h5>
<p>Code object V3 metadata is specified by the <code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code> note record
(see <a class="reference internal" href="#amdgpu-note-records-v3"><span class="std std-ref">Code Object V3 Note Records (-mattr=+code-object-v3)</span></a>).</p>
<p>The metadata is represented as Message Pack formatted binary data (see
<a class="reference internal" href="#msgpack" id="id28">[MsgPack]</a>). The top level is a Message Pack map that includes the
keys defined in table
<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Metadata Map</span></a> and referenced
tables.</p>
<p>Additional information can be added to the maps. To avoid conflicts,
any key names should be prefixed by “<em>vendor-name</em>.” where
<code class="docutils literal notranslate"><span class="pre">vendor-name</span></code> can be the the name of the vendor and specific vendor
tool that generates the information. The prefix is abbreviated to
simply “.” when it appears within a map that has been added by the
same <em>vendor-name</em>.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-map-table-v3">
<caption><span class="caption-text">AMDHSA Code Object V3 Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="17%" />
<col width="14%" />
<col width="9%" />
<col width="60%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“amdhsa.version”</td>
<td>sequence of
2 integers</td>
<td>Required</td>
<td><ul class="first last simple">
<li>The first integer is the major
version. Currently 1.</li>
<li>The second integer is the minor
version. Currently 0.</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>“amdhsa.printf”</td>
<td>sequence of
strings</td>
<td> </td>
<td><p class="first">Each string is encoded information
about a printf function call. The
encoded information is organized as
fields separated by colon (‘:’):</p>
<p><code class="docutils literal notranslate"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
<p>where:</p>
<dl class="last docutils">
<dt><code class="docutils literal notranslate"><span class="pre">ID</span></code></dt>
<dd>A 32 bit integer as a unique id for
each printf function call</dd>
<dt><code class="docutils literal notranslate"><span class="pre">N</span></code></dt>
<dd>A 32 bit integer equal to the number
of arguments of printf function call
minus 1</dd>
<dt><code class="docutils literal notranslate"><span class="pre">S[i]</span></code> (where i = 0, 1, … , N-1)</dt>
<dd>32 bit integers for the size in bytes
of the i-th FormatString argument of
the printf function call</dd>
<dt>FormatString</dt>
<dd>The format string passed to the
printf function call.</dd>
</dl>
</td>
</tr>
<tr class="row-even"><td>“amdhsa.kernels”</td>
<td>sequence of
map</td>
<td>Required</td>
<td>Sequence of the maps for each
kernel in the code object. See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Kernel Metadata Map</span></a>
for the definition of the keys included
in that map.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3">
<caption><span class="caption-text">AMDHSA Code Object V3 Kernel Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="27%" />
<col width="11%" />
<col width="7%" />
<col width="55%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“.name”</td>
<td>string</td>
<td>Required</td>
<td>Source name of the kernel.</td>
</tr>
<tr class="row-odd"><td>“.symbol”</td>
<td>string</td>
<td>Required</td>
<td>Name of the kernel
descriptor ELF symbol.</td>
</tr>
<tr class="row-even"><td>“.language”</td>
<td>string</td>
<td> </td>
<td><p class="first">Source language of the kernel.
Values include:</p>
<ul class="last simple">
<li>“OpenCL C”</li>
<li>“OpenCL C++”</li>
<li>“HCC”</li>
<li>“HIP”</li>
<li>“OpenMP”</li>
<li>“Assembler”</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>“.language_version”</td>
<td>sequence of
2 integers</td>
<td> </td>
<td><ul class="first last simple">
<li>The first integer is the major
version.</li>
<li>The second integer is the
minor version.</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“.args”</td>
<td>sequence of
map</td>
<td> </td>
<td>Sequence of maps of the
kernel arguments. See
<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Kernel Argument Metadata Map</span></a>
for the definition of the keys
included in that map.</td>
</tr>
<tr class="row-odd"><td>“.reqd_workgroup_size”</td>
<td>sequence of
3 integers</td>
<td> </td>
<td><p class="first">If not 0, 0, 0 then all values
must be >=1 and the dispatch
work-group size X, Y, Z must
correspond to the specified
values. Defaults to 0, 0, 0.</p>
<p class="last">Corresponds to the OpenCL
<code class="docutils literal notranslate"><span class="pre">reqd_work_group_size</span></code>
attribute.</p>
</td>
</tr>
<tr class="row-even"><td>“.workgroup_size_hint”</td>
<td>sequence of
3 integers</td>
<td> </td>
<td><p class="first">The dispatch work-group size
X, Y, Z is likely to be the
specified values.</p>
<p class="last">Corresponds to the OpenCL
<code class="docutils literal notranslate"><span class="pre">work_group_size_hint</span></code>
attribute.</p>
</td>
</tr>
<tr class="row-odd"><td>“.vec_type_hint”</td>
<td>string</td>
<td> </td>
<td><p class="first">The name of a scalar or vector
type.</p>
<p class="last">Corresponds to the OpenCL
<code class="docutils literal notranslate"><span class="pre">vec_type_hint</span></code> attribute.</p>
</td>
</tr>
<tr class="row-even"><td>“.device_enqueue_symbol”</td>
<td>string</td>
<td> </td>
<td>The external symbol name
associated with a kernel.
OpenCL runtime allocates a
global buffer for the symbol
and saves the kernel’s address
to it, which is used for
device side enqueueing. Only
available for device side
enqueued kernels.</td>
</tr>
<tr class="row-odd"><td>“.kernarg_segment_size”</td>
<td>integer</td>
<td>Required</td>
<td>The size in bytes of
the kernarg segment
that holds the values
of the arguments to
the kernel.</td>
</tr>
<tr class="row-even"><td>“.group_segment_fixed_size”</td>
<td>integer</td>
<td>Required</td>
<td>The amount of group
segment memory
required by a
work-group in
bytes. This does not
include any
dynamically allocated
group segment memory
that may be added
when the kernel is
dispatched.</td>
</tr>
<tr class="row-odd"><td>“.private_segment_fixed_size”</td>
<td>integer</td>
<td>Required</td>
<td>The amount of fixed
private address space
memory required for a
work-item in
bytes. If the kernel
uses a dynamic call
stack then additional
space must be added
to this value for the
call stack.</td>
</tr>
<tr class="row-even"><td>“.kernarg_segment_align”</td>
<td>integer</td>
<td>Required</td>
<td>The maximum byte
alignment of
arguments in the
kernarg segment. Must
be a power of 2.</td>
</tr>
<tr class="row-odd"><td>“.wavefront_size”</td>
<td>integer</td>
<td>Required</td>
<td>Wavefront size. Must
be a power of 2.</td>
</tr>
<tr class="row-even"><td>“.sgpr_count”</td>
<td>integer</td>
<td>Required</td>
<td>Number of scalar
registers required by a
wavefront for
GFX6-GFX9. A register
is required if it is
used explicitly, or
if a higher numbered
register is used
explicitly. This
includes the special
SGPRs for VCC, Flat
Scratch (GFX7-GFX9)
and XNACK (for
GFX8-GFX9). It does
not include the 16
SGPR added if a trap
handler is
enabled. It is not
rounded up to the
allocation
granularity.</td>
</tr>
<tr class="row-odd"><td>“.vgpr_count”</td>
<td>integer</td>
<td>Required</td>
<td>Number of vector
registers required by
each work-item for
GFX6-GFX9. A register
is required if it is
used explicitly, or
if a higher numbered
register is used
explicitly.</td>
</tr>
<tr class="row-even"><td>“.max_flat_workgroup_size”</td>
<td>integer</td>
<td>Required</td>
<td>Maximum flat
work-group size
supported by the
kernel in work-items.
Must be >=1 and
consistent with
ReqdWorkGroupSize if
not 0, 0, 0.</td>
</tr>
<tr class="row-odd"><td>“.sgpr_spill_count”</td>
<td>integer</td>
<td> </td>
<td>Number of stores from
a scalar register to
a register allocator
created spill
location.</td>
</tr>
<tr class="row-even"><td>“.vgpr_spill_count”</td>
<td>integer</td>
<td> </td>
<td>Number of stores from
a vector register to
a register allocator
created spill
location.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3">
<caption><span class="caption-text">AMDHSA Code Object V3 Kernel Argument Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="26%" />
<col width="17%" />
<col width="11%" />
<col width="46%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">String Key</th>
<th class="head">Value Type</th>
<th class="head">Required?</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>“.name”</td>
<td>string</td>
<td> </td>
<td>Kernel argument name.</td>
</tr>
<tr class="row-odd"><td>“.type_name”</td>
<td>string</td>
<td> </td>
<td>Kernel argument type name.</td>
</tr>
<tr class="row-even"><td>“.size”</td>
<td>integer</td>
<td>Required</td>
<td>Kernel argument size in bytes.</td>
</tr>
<tr class="row-odd"><td>“.offset”</td>
<td>integer</td>
<td>Required</td>
<td>Kernel argument offset in
bytes. The offset must be a
multiple of the alignment
required by the argument.</td>
</tr>
<tr class="row-even"><td>“.value_kind”</td>
<td>string</td>
<td>Required</td>
<td><p class="first">Kernel argument kind that
specifies how to set up the
corresponding argument.
Values include:</p>
<dl class="last docutils">
<dt>“by_value”</dt>
<dd>The argument is copied
directly into the kernarg.</dd>
<dt>“global_buffer”</dt>
<dd>A global address space pointer
to the buffer data is passed
in the kernarg.</dd>
<dt>“dynamic_shared_pointer”</dt>
<dd>A group address space pointer
to dynamically allocated LDS
is passed in the kernarg.</dd>
<dt>“sampler”</dt>
<dd>A global address space
pointer to a S# is passed in
the kernarg.</dd>
<dt>“image”</dt>
<dd>A global address space
pointer to a T# is passed in
the kernarg.</dd>
<dt>“pipe”</dt>
<dd>A global address space pointer
to an OpenCL pipe is passed in
the kernarg.</dd>
<dt>“queue”</dt>
<dd>A global address space pointer
to an OpenCL device enqueue
queue is passed in the
kernarg.</dd>
<dt>“hidden_global_offset_x”</dt>
<dd>The OpenCL grid dispatch
global offset for the X
dimension is passed in the
kernarg.</dd>
<dt>“hidden_global_offset_y”</dt>
<dd>The OpenCL grid dispatch
global offset for the Y
dimension is passed in the
kernarg.</dd>
<dt>“hidden_global_offset_z”</dt>
<dd>The OpenCL grid dispatch
global offset for the Z
dimension is passed in the
kernarg.</dd>
<dt>“hidden_none”</dt>
<dd>An argument that is not used
by the kernel. Space needs to
be left for it, but it does
not need to be set up.</dd>
<dt>“hidden_printf_buffer”</dt>
<dd>A global address space pointer
to the runtime printf buffer
is passed in kernarg.</dd>
<dt>“hidden_default_queue”</dt>
<dd>A global address space pointer
to the OpenCL device enqueue
queue that should be used by
the kernel by default is
passed in the kernarg.</dd>
<dt>“hidden_completion_action”</dt>
<dd>A global address space pointer
to help link enqueued kernels into
the ancestor tree for determining
when the parent kernel has finished.</dd>
</dl>
</td>
</tr>
<tr class="row-odd"><td>“.value_type”</td>
<td>string</td>
<td>Required</td>
<td><p class="first">Kernel argument value type. Only
present if “.value_kind” is
“by_value”. For vector data
types, the value is for the
element type. Values include:</p>
<ul class="last simple">
<li>“struct”</li>
<li>“i8”</li>
<li>“u8”</li>
<li>“i16”</li>
<li>“u16”</li>
<li>“f16”</li>
<li>“i32”</li>
<li>“u32”</li>
<li>“f32”</li>
<li>“i64”</li>
<li>“u64”</li>
<li>“f64”</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“.pointee_align”</td>
<td>integer</td>
<td> </td>
<td>Alignment in bytes of pointee
type for pointer type kernel
argument. Must be a power
of 2. Only present if
“.value_kind” is
“dynamic_shared_pointer”.</td>
</tr>
<tr class="row-odd"><td>“.address_space”</td>
<td>string</td>
<td> </td>
<td><p class="first">Kernel argument address space
qualifier. Only present if
“.value_kind” is “global_buffer” or
“dynamic_shared_pointer”. Values
are:</p>
<ul class="last simple">
<li>“private”</li>
<li>“global”</li>
<li>“constant”</li>
<li>“local”</li>
<li>“generic”</li>
<li>“region”</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“.access”</td>
<td>string</td>
<td> </td>
<td><p class="first">Kernel argument access
qualifier. Only present if
“.value_kind” is “image” or
“pipe”. Values
are:</p>
<ul class="last simple">
<li>“read_only”</li>
<li>“write_only”</li>
<li>“read_write”</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>“.actual_access”</td>
<td>string</td>
<td> </td>
<td><p class="first">The actual memory accesses
performed by the kernel on the
kernel argument. Only present if
“.value_kind” is “global_buffer”,
“image”, or “pipe”. This may be
more restrictive than indicated
by “.access” to reflect what the
kernel actual does. If not
present then the runtime must
assume what is implied by
“.access” and “.is_const” . Values
are:</p>
<ul class="last simple">
<li>“read_only”</li>
<li>“write_only”</li>
<li>“read_write”</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>“.is_const”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is const qualified. Only present
if “.value_kind” is
“global_buffer”.</td>
</tr>
<tr class="row-odd"><td>“.is_restrict”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is restrict qualified. Only
present if “.value_kind” is
“global_buffer”.</td>
</tr>
<tr class="row-even"><td>“.is_volatile”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is volatile qualified. Only
present if “.value_kind” is
“global_buffer”.</td>
</tr>
<tr class="row-odd"><td>“.is_pipe”</td>
<td>boolean</td>
<td> </td>
<td>Indicates if the kernel argument
is pipe qualified. Only present
if “.value_kind” is “pipe”.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="kernel-dispatch">
<h4><a class="toc-backref" href="#id73">Kernel Dispatch</a><a class="headerlink" href="#kernel-dispatch" title="Permalink to this headline">¶</a></h4>
<p>The HSA architected queuing language (AQL) defines a user space memory interface
that can be used to control the dispatch of kernels, in an agent independent
way. An agent can have zero or more AQL queues created for it using the ROCm
runtime, in which AQL packets (all of which are 64 bytes) can be placed. See the
<em>HSA Platform System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id29">[HSA]</a> for the AQL queue
mechanics and packet layouts.</p>
<p>The packet processor of a kernel agent is responsible for detecting and
dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
packet processor is implemented by the hardware command processor (CP),
asynchronous dispatch controller (ADC) and shader processor input controller
(SPI).</p>
<p>The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel
mode driver to initialize and register the AQL queue with CP.</p>
<p>To dispatch a kernel the following actions are performed. This can occur in the
CPU host program, or from an HSA kernel executing on a GPU.</p>
<ol class="arabic simple">
<li>A pointer to an AQL queue for the kernel agent on which the kernel is to be
executed is obtained.</li>
<li>A pointer to the kernel descriptor (see
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>) of the kernel to execute is
obtained. It must be for a kernel that is contained in a code object that that
was loaded by the ROCm runtime on the kernel agent with which the AQL queue is
associated.</li>
<li>Space is allocated for the kernel arguments using the ROCm runtime allocator
for a memory region with the kernarg property for the kernel agent that will
execute the kernel. It must be at least 16 byte aligned.</li>
<li>Kernel argument values are assigned to the kernel argument memory
allocation. The layout is defined in the <em>HSA Programmer’s Language Reference</em>
<a class="reference internal" href="#hsa" id="id30">[HSA]</a>. For AMDGPU the kernel execution directly accesses the kernel argument
memory in the same way constant memory is accessed. (Note that the HSA
specification allows an implementation to copy the kernel argument contents to
another location that is accessed by the kernel.)</li>
<li>An AQL kernel dispatch packet is created on the AQL queue. The ROCm runtime
api uses 64 bit atomic operations to reserve space in the AQL queue for the
packet. The packet must be set up, and the final write must use an atomic
store release to set the packet kind to ensure the packet contents are
visible to the kernel agent. AQL defines a doorbell signal mechanism to
notify the kernel agent that the AQL queue has been updated. These rules, and
the layout of the AQL queue and kernel dispatch packet is defined in the <em>HSA
System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id31">[HSA]</a>.</li>
<li>A kernel dispatch packet includes information about the actual dispatch,
such as grid and work-group size, together with information from the code
object about the kernel, such as segment sizes. The ROCm runtime queries on
the kernel symbol can be used to obtain the code object values which are
recorded in the <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>.</li>
<li>CP executes micro-code and is responsible for detecting and setting up the
GPU to execute the wavefronts of a kernel dispatch.</li>
<li>CP ensures that when the a wavefront starts executing the kernel machine
code, the scalar general purpose registers (SGPR) and vector general purpose
registers (VGPR) are set up as required by the machine code. The required
setup is defined in the <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. The initial
register state is defined in
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>.</li>
<li>The prolog of the kernel machine code (see
<a class="reference internal" href="#amdgpu-amdhsa-kernel-prolog"><span class="std std-ref">Kernel Prolog</span></a>) sets up the machine state as necessary
before continuing executing the machine code that corresponds to the kernel.</li>
<li>When the kernel dispatch has completed execution, CP signals the completion
signal specified in the kernel dispatch packet if not 0.</li>
</ol>
</div>
<div class="section" id="memory-spaces">
<span id="amdgpu-amdhsa-memory-spaces"></span><h4><a class="toc-backref" href="#id74">Memory Spaces</a><a class="headerlink" href="#memory-spaces" title="Permalink to this headline">¶</a></h4>
<p>The memory space properties are:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-spaces-table">
<caption><span class="caption-text">AMDHSA Memory Spaces</span><a class="headerlink" href="#amdgpu-amdhsa-memory-spaces-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="28%" />
<col width="18%" />
<col width="13%" />
<col width="11%" />
<col width="30%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Memory Space Name</th>
<th class="head">HSA Segment
Name</th>
<th class="head">Hardware
Name</th>
<th class="head">Address
Size</th>
<th class="head">NULL Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>Private</td>
<td>private</td>
<td>scratch</td>
<td>32</td>
<td>0x00000000</td>
</tr>
<tr class="row-odd"><td>Local</td>
<td>group</td>
<td>LDS</td>
<td>32</td>
<td>0xFFFFFFFF</td>
</tr>
<tr class="row-even"><td>Global</td>
<td>global</td>
<td>global</td>
<td>64</td>
<td>0x0000000000000000</td>
</tr>
<tr class="row-odd"><td>Constant</td>
<td>constant</td>
<td><em>same as
global</em></td>
<td>64</td>
<td>0x0000000000000000</td>
</tr>
<tr class="row-even"><td>Generic</td>
<td>flat</td>
<td>flat</td>
<td>64</td>
<td>0x0000000000000000</td>
</tr>
<tr class="row-odd"><td>Region</td>
<td>N/A</td>
<td>GDS</td>
<td>32</td>
<td><em>not implemented
for AMDHSA</em></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>The global and constant memory spaces both use global virtual addresses, which
are the same virtual address space used by the CPU. However, some virtual
addresses may only be accessible to the CPU, some only accessible by the GPU,
and some by both.</p>
<p>Using the constant memory space indicates that the data will not change during
the execution of the kernel. This allows scalar read instructions to be
used. The vector and scalar L1 caches are invalidated of volatile data before
each kernel dispatch execution to allow constant memory to change values between
kernel dispatches.</p>
<p>The local memory space uses the hardware Local Data Store (LDS) which is
automatically allocated when the hardware creates work-groups of wavefronts, and
freed when all the wavefronts of a work-group have terminated. The data store
(DS) instructions can be used to access it.</p>
<p>The private memory space uses the hardware scratch memory support. If the kernel
uses scratch, then the hardware allocates memory that is accessed using
wavefront lane dword (4 byte) interleaving. The mapping used from private
address to physical address is:</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre">wavefront-scratch-base</span> <span class="pre">+</span>
<span class="pre">(private-address</span> <span class="pre">*</span> <span class="pre">wavefront-size</span> <span class="pre">*</span> <span class="pre">4)</span> <span class="pre">+</span>
<span class="pre">(wavefront-lane-id</span> <span class="pre">*</span> <span class="pre">4)</span></code></div></blockquote>
<p>There are different ways that the wavefront scratch base address is determined
by a wavefront (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). This
memory can be accessed in an interleaved manner using buffer instruction with
the scratch buffer descriptor and per wavefront scratch offset, by the scratch
instructions, or by flat instructions. If each lane of a wavefront accesses the
same private address, the interleaving results in adjacent dwords being accessed
and hence requires fewer cache lines to be fetched. Multi-dword access is not
supported except by flat and scratch instructions in GFX9.</p>
<p>The generic address space uses the hardware flat address support available in
GFX7-GFX9. This uses two fixed ranges of virtual addresses (the private and
local appertures), that are outside the range of addressible global memory, to
map from a flat address to a private or local address.</p>
<p>FLAT instructions can take a flat address and access global, private (scratch)
and group (LDS) memory depending in if the address is within one of the
apperture ranges. Flat access to scratch requires hardware aperture setup and
setup in the kernel prologue (see <a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>). Flat
access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup
(see <a class="reference internal" href="#amdgpu-amdhsa-m0"><span class="std std-ref">M0</span></a>).</p>
<p>To convert between a segment address and a flat address the base address of the
appertures address can be used. For GFX7-GFX8 these are available in the
<a class="reference internal" href="#amdgpu-amdhsa-hsa-aql-queue"><span class="std std-ref">HSA AQL Queue</span></a> the address of which can be obtained with
Queue Ptr SGPR (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). For
GFX9 the appature base addresses are directly available as inline constant
registers <code class="docutils literal notranslate"><span class="pre">SRC_SHARED_BASE/LIMIT</span></code> and <code class="docutils literal notranslate"><span class="pre">SRC_PRIVATE_BASE/LIMIT</span></code>. In 64 bit
address mode the apperture sizes are 2^32 bytes and the base is aligned to 2^32
which makes it easier to convert from flat to segment or segment to flat.</p>
</div>
<div class="section" id="image-and-samplers">
<h4><a class="toc-backref" href="#id75">Image and Samplers</a><a class="headerlink" href="#image-and-samplers" title="Permalink to this headline">¶</a></h4>
<p>Image and sample handles created by the ROCm runtime are 64 bit addresses of a
hardware 32 byte V# and 48 byte S# object respectively. In order to support the
HSA <code class="docutils literal notranslate"><span class="pre">query_sampler</span></code> operations two extra dwords are used to store the HSA BRIG
enumeration values for the queries that are not trivially deducible from the S#
representation.</p>
</div>
<div class="section" id="hsa-signals">
<h4><a class="toc-backref" href="#id76">HSA Signals</a><a class="headerlink" href="#hsa-signals" title="Permalink to this headline">¶</a></h4>
<p>HSA signal handles created by the ROCm runtime are 64 bit addresses of a
structure allocated in memory accessible from both the CPU and GPU. The
structure is defined by the ROCm runtime and subject to change between releases
(see <a class="reference internal" href="#amd-rocm-github" id="id32">[AMD-ROCm-github]</a>).</p>
</div>
<div class="section" id="hsa-aql-queue">
<span id="amdgpu-amdhsa-hsa-aql-queue"></span><h4><a class="toc-backref" href="#id77">HSA AQL Queue</a><a class="headerlink" href="#hsa-aql-queue" title="Permalink to this headline">¶</a></h4>
<p>The HSA AQL queue structure is defined by the ROCm runtime and subject to change
between releases (see <a class="reference internal" href="#amd-rocm-github" id="id33">[AMD-ROCm-github]</a>). For some processors it contains
fields needed to implement certain language features such as the flat address
aperture bases. It also contains fields used by CP such as managing the
allocation of scratch memory.</p>
</div>
<div class="section" id="kernel-descriptor">
<span id="amdgpu-amdhsa-kernel-descriptor"></span><h4><a class="toc-backref" href="#id78">Kernel Descriptor</a><a class="headerlink" href="#kernel-descriptor" title="Permalink to this headline">¶</a></h4>
<p>A kernel descriptor consists of the information needed by CP to initiate the
execution of a kernel, including the entry point address of the machine code
that implements the kernel.</p>
<div class="section" id="kernel-descriptor-for-gfx6-gfx9">
<h5><a class="toc-backref" href="#id79">Kernel Descriptor for GFX6-GFX9</a><a class="headerlink" href="#kernel-descriptor-for-gfx6-gfx9" title="Permalink to this headline">¶</a></h5>
<p>CP microcode requires the Kernel descriptor to be allocated on 64 byte
alignment.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table">
<caption><span class="caption-text">Kernel Descriptor for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="7%" />
<col width="7%" />
<col width="31%" />
<col width="55%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Bits</th>
<th class="head">Size</th>
<th class="head">Field Name</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>31:0</td>
<td>4 bytes</td>
<td>GROUP_SEGMENT_FIXED_SIZE</td>
<td>The amount of fixed local
address space memory
required for a work-group
in bytes. This does not
include any dynamically
allocated local address
space memory that may be
added when the kernel is
dispatched.</td>
</tr>
<tr class="row-odd"><td>63:32</td>
<td>4 bytes</td>
<td>PRIVATE_SEGMENT_FIXED_SIZE</td>
<td>The amount of fixed
private address space
memory required for a
work-item in bytes. If
is_dynamic_callstack is 1
then additional space must
be added to this value for
the call stack.</td>
</tr>
<tr class="row-even"><td>127:64</td>
<td>8 bytes</td>
<td> </td>
<td>Reserved, must be 0.</td>
</tr>
<tr class="row-odd"><td>191:128</td>
<td>8 bytes</td>
<td>KERNEL_CODE_ENTRY_BYTE_OFFSET</td>
<td>Byte offset (possibly
negative) from base
address of kernel
descriptor to kernel’s
entry point instruction
which must be 256 byte
aligned.</td>
</tr>
<tr class="row-even"><td>383:192</td>
<td>24
bytes</td>
<td> </td>
<td>Reserved, must be 0.</td>
</tr>
<tr class="row-odd"><td>415:384</td>
<td>4 bytes</td>
<td>COMPUTE_PGM_RSRC1</td>
<td>Compute Shader (CS)
program settings used by
CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1</span></code>
configuration
register. See
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td>447:416</td>
<td>4 bytes</td>
<td>COMPUTE_PGM_RSRC2</td>
<td>Compute Shader (CS)
program settings used by
CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2</span></code>
configuration
register. See
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td>448</td>
<td>1 bit</td>
<td>ENABLE_SGPR_PRIVATE_SEGMENT
_BUFFER</td>
<td><p class="first">Enable the setup of the
SGPR user data registers
(see
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
<p class="last">The total number of SGPR
user data registers
requested must not exceed
16 and match value in
<code class="docutils literal notranslate"><span class="pre">compute_pgm_rsrc2.user_sgpr.user_sgpr_count</span></code>.
Any requests beyond 16
will be ignored.</p>
</td>
</tr>
<tr class="row-even"><td>449</td>
<td>1 bit</td>
<td>ENABLE_SGPR_DISPATCH_PTR</td>
<td><em>see above</em></td>
</tr>
<tr class="row-odd"><td>450</td>
<td>1 bit</td>
<td>ENABLE_SGPR_QUEUE_PTR</td>
<td><em>see above</em></td>
</tr>
<tr class="row-even"><td>451</td>
<td>1 bit</td>
<td>ENABLE_SGPR_KERNARG_SEGMENT_PTR</td>
<td><em>see above</em></td>
</tr>
<tr class="row-odd"><td>452</td>
<td>1 bit</td>
<td>ENABLE_SGPR_DISPATCH_ID</td>
<td><em>see above</em></td>
</tr>
<tr class="row-even"><td>453</td>
<td>1 bit</td>
<td>ENABLE_SGPR_FLAT_SCRATCH_INIT</td>
<td><em>see above</em></td>
</tr>
<tr class="row-odd"><td>454</td>
<td>1 bit</td>
<td>ENABLE_SGPR_PRIVATE_SEGMENT
_SIZE</td>
<td><em>see above</em></td>
</tr>
<tr class="row-even"><td>455</td>
<td>1 bit</td>
<td> </td>
<td>Reserved, must be 0.</td>
</tr>
<tr class="row-odd"><td>511:456</td>
<td>8 bytes</td>
<td> </td>
<td>Reserved, must be 0.</td>
</tr>
<tr class="row-even"><td>512</td>
<td colspan="3"><strong>Total size 64 bytes.</strong></td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table">
<caption><span class="caption-text">compute_pgm_rsrc1 for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="6%" />
<col width="6%" />
<col width="26%" />
<col width="63%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Bits</th>
<th class="head">Size</th>
<th class="head">Field Name</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>5:0</td>
<td>6 bits</td>
<td>GRANULATED_WORKITEM_VGPR_COUNT</td>
<td><p class="first">Number of vector register
blocks used by each work-item;
granularity is device
specific:</p>
<dl class="docutils">
<dt>GFX6-GFX9</dt>
<dd><ul class="first last simple">
<li>vgprs_used 0..256</li>
<li>max(0, ceil(vgprs_used / 4) - 1)</li>
</ul>
</dd>
</dl>
<p>Where vgprs_used is defined
as the highest VGPR number
explicitly referenced plus
one.</p>
<p>Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.VGPRS</span></code>.</p>
<p class="last">The
<a class="reference internal" href="#amdgpu-assembler"><span class="std std-ref">Assembler</span></a>
calculates this
automatically for the
selected processor from
values provided to the
<cite>.amdhsa_kernel</cite> directive
by the
<cite>.amdhsa_next_free_vgpr</cite>
nested directive (see
<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>).</p>
</td>
</tr>
<tr class="row-odd"><td>9:6</td>
<td>4 bits</td>
<td>GRANULATED_WAVEFRONT_SGPR_COUNT</td>
<td><p class="first">Number of scalar register
blocks used by a wavefront;
granularity is device
specific:</p>
<dl class="docutils">
<dt>GFX6-GFX8</dt>
<dd><ul class="first last simple">
<li>sgprs_used 0..112</li>
<li>max(0, ceil(sgprs_used / 8) - 1)</li>
</ul>
</dd>
<dt>GFX9</dt>
<dd><ul class="first last simple">
<li>sgprs_used 0..112</li>
<li>2 * max(0, ceil(sgprs_used / 16) - 1)</li>
</ul>
</dd>
</dl>
<p>Where sgprs_used is
defined as the highest
SGPR number explicitly
referenced plus one, plus
a target-specific number
of additional special
SGPRs for VCC,
FLAT_SCRATCH (GFX7+) and
XNACK_MASK (GFX8+), and
any additional
target-specific
limitations. It does not
include the 16 SGPRs added
if a trap handler is
enabled.</p>
<p>The target-specific
limitations and special
SGPR layout are defined in
the hardware
documentation, which can
be found in the
<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>
table.</p>
<p>Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.SGPRS</span></code>.</p>
<p class="last">The
<a class="reference internal" href="#amdgpu-assembler"><span class="std std-ref">Assembler</span></a>
calculates this
automatically for the
selected processor from
values provided to the
<cite>.amdhsa_kernel</cite> directive
by the
<cite>.amdhsa_next_free_sgpr</cite>
and <cite>.amdhsa_reserve_*</cite>
nested directives (see
<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>).</p>
</td>
</tr>
<tr class="row-even"><td>11:10</td>
<td>2 bits</td>
<td>PRIORITY</td>
<td><p class="first">Must be 0.</p>
<p>Start executing wavefront
at the specified priority.</p>
<p class="last">CP is responsible for
filling in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.PRIORITY</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>13:12</td>
<td>2 bits</td>
<td>FLOAT_ROUND_MODE_32</td>
<td><p class="first">Wavefront starts execution
with specified rounding
mode for single (32
bit) floating point
precision floating point
operations.</p>
<p>Floating point rounding
mode values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>15:14</td>
<td>2 bits</td>
<td>FLOAT_ROUND_MODE_16_64</td>
<td><p class="first">Wavefront starts execution
with specified rounding
denorm mode for half/double (16
and 64 bit) floating point
precision floating point
operations.</p>
<p>Floating point rounding
mode values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>17:16</td>
<td>2 bits</td>
<td>FLOAT_DENORM_MODE_32</td>
<td><p class="first">Wavefront starts execution
with specified denorm mode
for single (32
bit) floating point
precision floating point
operations.</p>
<p>Floating point denorm mode
values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>19:18</td>
<td>2 bits</td>
<td>FLOAT_DENORM_MODE_16_64</td>
<td><p class="first">Wavefront starts execution
with specified denorm mode
for half/double (16
and 64 bit) floating point
precision floating point
operations.</p>
<p>Floating point denorm mode
values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>20</td>
<td>1 bit</td>
<td>PRIV</td>
<td><p class="first">Must be 0.</p>
<p>Start executing wavefront
in privilege trap handler
mode.</p>
<p class="last">CP is responsible for
filling in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.PRIV</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>21</td>
<td>1 bit</td>
<td>ENABLE_DX10_CLAMP</td>
<td><p class="first">Wavefront starts execution
with DX10 clamp mode
enabled. Used by the vector
ALU to force DX10 style
treatment of NaN’s (when
set, clamp NaN to zero,
otherwise pass NaN
through).</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.DX10_CLAMP</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>22</td>
<td>1 bit</td>
<td>DEBUG_MODE</td>
<td><p class="first">Must be 0.</p>
<p>Start executing wavefront
in single step mode.</p>
<p class="last">CP is responsible for
filling in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.DEBUG_MODE</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>23</td>
<td>1 bit</td>
<td>ENABLE_IEEE_MODE</td>
<td><p class="first">Wavefront starts execution
with IEEE mode
enabled. Floating point
opcodes that support
exception flag gathering
will quiet and propagate
signaling-NaN inputs per
IEEE 754-2008. Min_dx10 and
max_dx10 become IEEE
754-2008 compliant due to
signaling-NaN propagation
and quieting.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.IEEE_MODE</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>24</td>
<td>1 bit</td>
<td>BULKY</td>
<td><p class="first">Must be 0.</p>
<p>Only one work-group allowed
to execute on a compute
unit.</p>
<p class="last">CP is responsible for
filling in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.BULKY</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>25</td>
<td>1 bit</td>
<td>CDBG_USER</td>
<td><p class="first">Must be 0.</p>
<p>Flag that can be used to
control debugging code.</p>
<p class="last">CP is responsible for
filling in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.CDBG_USER</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>26</td>
<td>1 bit</td>
<td>FP16_OVFL</td>
<td><dl class="first last docutils">
<dt>GFX6-GFX8</dt>
<dd>Reserved, must be 0.</dd>
<dt>GFX9</dt>
<dd><p class="first">Wavefront starts execution
with specified fp16 overflow
mode.</p>
<ul class="simple">
<li>If 0, fp16 overflow generates
+/-INF values.</li>
<li>If 1, fp16 overflow that is the
result of an +/-INF input value
or divide by 0 produces a +/-INF,
otherwise clamps computed
overflow to +/-MAX_FP16 as
appropriate.</li>
</ul>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FP16_OVFL</span></code>.</p>
</dd>
</dl>
</td>
</tr>
<tr class="row-even"><td>31:27</td>
<td>5 bits</td>
<td> </td>
<td>Reserved, must be 0.</td>
</tr>
<tr class="row-odd"><td>32</td>
<td colspan="3"><strong>Total size 4 bytes</strong></td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table">
<caption><span class="caption-text">compute_pgm_rsrc2 for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="6%" />
<col width="6%" />
<col width="26%" />
<col width="63%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Bits</th>
<th class="head">Size</th>
<th class="head">Field Name</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>0</td>
<td>1 bit</td>
<td>ENABLE_SGPR_PRIVATE_SEGMENT
_WAVEFRONT_OFFSET</td>
<td><p class="first">Enable the setup of the
SGPR wavefront scratch offset
system register (see
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.SCRATCH_EN</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>5:1</td>
<td>5 bits</td>
<td>USER_SGPR_COUNT</td>
<td><p class="first">The total number of SGPR
user data registers
requested. This number must
match the number of user
data registers enabled.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.USER_SGPR</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>6</td>
<td>1 bit</td>
<td>ENABLE_TRAP_HANDLER</td>
<td><p class="first">Must be 0.</p>
<p class="last">This bit represents
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TRAP_PRESENT</span></code>,
which is set by the CP if
the runtime has installed a
trap handler.</p>
</td>
</tr>
<tr class="row-odd"><td>7</td>
<td>1 bit</td>
<td>ENABLE_SGPR_WORKGROUP_ID_X</td>
<td><p class="first">Enable the setup of the
system SGPR register for
the work-group id in the X
dimension (see
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_X_EN</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>8</td>
<td>1 bit</td>
<td>ENABLE_SGPR_WORKGROUP_ID_Y</td>
<td><p class="first">Enable the setup of the
system SGPR register for
the work-group id in the Y
dimension (see
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Y_EN</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>9</td>
<td>1 bit</td>
<td>ENABLE_SGPR_WORKGROUP_ID_Z</td>
<td><p class="first">Enable the setup of the
system SGPR register for
the work-group id in the Z
dimension (see
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Z_EN</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>10</td>
<td>1 bit</td>
<td>ENABLE_SGPR_WORKGROUP_INFO</td>
<td><p class="first">Enable the setup of the
system SGPR register for
work-group information (see
<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_SIZE_EN</span></code>.</p>
</td>
</tr>
<tr class="row-odd"><td>12:11</td>
<td>2 bits</td>
<td>ENABLE_VGPR_WORKITEM_ID</td>
<td><p class="first">Enable the setup of the
VGPR system registers used
for the work-item ID.
<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>
defines the values.</p>
<p class="last">Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT</span></code>.</p>
</td>
</tr>
<tr class="row-even"><td>13</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_ADDRESS_WATCH</td>
<td><p class="first">Must be 0.</p>
<p>Wavefront starts execution
with address watch
exceptions enabled which
are generated when L1 has
witnessed a thread access
an <em>address of
interest</em>.</p>
<p class="last">CP is responsible for
filling in the address
watch bit in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
according to what the
runtime requests.</p>
</td>
</tr>
<tr class="row-odd"><td>14</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_MEMORY</td>
<td><p class="first">Must be 0.</p>
<p>Wavefront starts execution
with memory violation
exceptions exceptions
enabled which are generated
when a memory violation has
occurred for this wavefront from
L1 or LDS
(write-to-read-only-memory,
mis-aligned atomic, LDS
address out of range,
illegal address, etc.).</p>
<p class="last">CP sets the memory
violation bit in
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
according to what the
runtime requests.</p>
</td>
</tr>
<tr class="row-even"><td>23:15</td>
<td>9 bits</td>
<td>GRANULATED_LDS_SIZE</td>
<td><p class="first">Must be 0.</p>
<p>CP uses the rounded value
from the dispatch packet,
not this value, as the
dispatch may contain
dynamically allocated group
segment memory. CP writes
directly to
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.LDS_SIZE</span></code>.</p>
<p>Amount of group segment
(LDS) to allocate for each
work-group. Granularity is
device specific:</p>
<dl class="last docutils">
<dt>GFX6:</dt>
<dd>roundup(lds-size / (64 * 4))</dd>
<dt>GFX7-GFX9:</dt>
<dd>roundup(lds-size / (128 * 4))</dd>
</dl>
</td>
</tr>
<tr class="row-odd"><td>24</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_IEEE_754_FP
_INVALID_OPERATION</td>
<td><p class="first">Wavefront starts execution
with specified exceptions
enabled.</p>
<p>Used by CP to set up
<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN</span></code>
(set from bits 0..6).</p>
<p class="last">IEEE 754 FP Invalid
Operation</p>
</td>
</tr>
<tr class="row-even"><td>25</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_FP_DENORMAL
_SOURCE</td>
<td>FP Denormal one or more
input operands is a
denormal number</td>
</tr>
<tr class="row-odd"><td>26</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_IEEE_754_FP
_DIVISION_BY_ZERO</td>
<td>IEEE 754 FP Division by
Zero</td>
</tr>
<tr class="row-even"><td>27</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_IEEE_754_FP
_OVERFLOW</td>
<td>IEEE 754 FP FP Overflow</td>
</tr>
<tr class="row-odd"><td>28</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_IEEE_754_FP
_UNDERFLOW</td>
<td>IEEE 754 FP Underflow</td>
</tr>
<tr class="row-even"><td>29</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_IEEE_754_FP
_INEXACT</td>
<td>IEEE 754 FP Inexact</td>
</tr>
<tr class="row-odd"><td>30</td>
<td>1 bit</td>
<td>ENABLE_EXCEPTION_INT_DIVIDE_BY
_ZERO</td>
<td>Integer Division by Zero
(rcp_iflag_f32 instruction
only)</td>
</tr>
<tr class="row-even"><td>31</td>
<td>1 bit</td>
<td> </td>
<td>Reserved, must be 0.</td>
</tr>
<tr class="row-odd"><td>32</td>
<td colspan="3"><strong>Total size 4 bytes.</strong></td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table">
<caption><span class="caption-text">Floating Point Rounding Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="52%" />
<col width="7%" />
<col width="41%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Enumeration Name</th>
<th class="head">Value</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>FLOAT_ROUND_MODE_NEAR_EVEN</td>
<td>0</td>
<td>Round Ties To Even</td>
</tr>
<tr class="row-odd"><td>FLOAT_ROUND_MODE_PLUS_INFINITY</td>
<td>1</td>
<td>Round Toward +infinity</td>
</tr>
<tr class="row-even"><td>FLOAT_ROUND_MODE_MINUS_INFINITY</td>
<td>2</td>
<td>Round Toward -infinity</td>
</tr>
<tr class="row-odd"><td>FLOAT_ROUND_MODE_ZERO</td>
<td>3</td>
<td>Round Toward 0</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table">
<caption><span class="caption-text">Floating Point Denorm Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="52%" />
<col width="7%" />
<col width="41%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Enumeration Name</th>
<th class="head">Value</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>FLOAT_DENORM_MODE_FLUSH_SRC_DST</td>
<td>0</td>
<td>Flush Source and Destination
Denorms</td>
</tr>
<tr class="row-odd"><td>FLOAT_DENORM_MODE_FLUSH_DST</td>
<td>1</td>
<td>Flush Output Denorms</td>
</tr>
<tr class="row-even"><td>FLOAT_DENORM_MODE_FLUSH_SRC</td>
<td>2</td>
<td>Flush Source Denorms</td>
</tr>
<tr class="row-odd"><td>FLOAT_DENORM_MODE_FLUSH_NONE</td>
<td>3</td>
<td>No Flush</td>
</tr>
</tbody>
</table>
</div></blockquote>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table">
<caption><span class="caption-text">System VGPR Work-Item ID Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="55%" />
<col width="7%" />
<col width="38%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Enumeration Name</th>
<th class="head">Value</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>SYSTEM_VGPR_WORKITEM_ID_X</td>
<td>0</td>
<td>Set work-item X dimension
ID.</td>
</tr>
<tr class="row-odd"><td>SYSTEM_VGPR_WORKITEM_ID_X_Y</td>
<td>1</td>
<td>Set work-item X and Y
dimensions ID.</td>
</tr>
<tr class="row-even"><td>SYSTEM_VGPR_WORKITEM_ID_X_Y_Z</td>
<td>2</td>
<td>Set work-item X, Y and Z
dimensions ID.</td>
</tr>
<tr class="row-odd"><td>SYSTEM_VGPR_WORKITEM_ID_UNDEFINED</td>
<td>3</td>
<td>Undefined.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="initial-kernel-execution-state">
<span id="amdgpu-amdhsa-initial-kernel-execution-state"></span><h4><a class="toc-backref" href="#id80">Initial Kernel Execution State</a><a class="headerlink" href="#initial-kernel-execution-state" title="Permalink to this headline">¶</a></h4>
<p>This section defines the register state that will be set up by the packet
processor prior to the start of execution of every wavefront. This is limited by
the constraints of the hardware controllers of CP/ADC/SPI.</p>
<p>The order of the SGPR registers is defined, but the compiler can specify which
ones are actually setup in the kernel descriptor using the <code class="docutils literal notranslate"><span class="pre">enable_sgpr_*</span></code> bit
fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
for enabled registers are dense starting at SGPR0: the first enabled register is
SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
an SGPR number.</p>
<p>The initial SGPRs comprise up to 16 User SRGPs that are set by CP and apply to
all wavefronts of the grid. It is possible to specify more than 16 User SGPRs using
the <code class="docutils literal notranslate"><span class="pre">enable_sgpr_*</span></code> bit fields, in which case only the first 16 are actually
initialized. These are then immediately followed by the System SGPRs that are
set up by ADC/SPI and can have different values for each wavefront of the grid
dispatch.</p>
<p>SGPR register initial state is defined in
<a class="reference internal" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table"><span class="std std-ref">SGPR Register Set Up Order</span></a>.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-sgpr-register-set-up-order-table">
<caption><span class="caption-text">SGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="13%" />
<col width="33%" />
<col width="8%" />
<col width="46%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">SGPR Order</th>
<th class="head">Name
(kernel descriptor enable
field)</th>
<th class="head">Number
of
SGPRs</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>First</td>
<td>Private Segment Buffer
(enable_sgpr_private
_segment_buffer)</td>
<td>4</td>
<td><p class="first">V# that can be used, together
with Scratch Wavefront Offset
as an offset, to access the
private memory space using a
segment address.</p>
<p class="last">CP uses the value provided by
the runtime.</p>
</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Dispatch Ptr
(enable_sgpr_dispatch_ptr)</td>
<td>2</td>
<td>64 bit address of AQL dispatch
packet for kernel dispatch
actually executing.</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Queue Ptr
(enable_sgpr_queue_ptr)</td>
<td>2</td>
<td>64 bit address of amd_queue_t
object for AQL queue on which
the dispatch packet was
queued.</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Kernarg Segment Ptr
(enable_sgpr_kernarg
_segment_ptr)</td>
<td>2</td>
<td><p class="first">64 bit address of Kernarg
segment. This is directly
copied from the
kernarg_address in the kernel
dispatch packet.</p>
<p class="last">Having CP load it once avoids
loading it at the beginning of
every wavefront.</p>
</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Dispatch Id
(enable_sgpr_dispatch_id)</td>
<td>2</td>
<td>64 bit Dispatch ID of the
dispatch packet being
executed.</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Flat Scratch Init
(enable_sgpr_flat_scratch
_init)</td>
<td>2</td>
<td><p class="first">This is 2 SGPRs:</p>
<dl class="last docutils">
<dt>GFX6</dt>
<dd>Not supported.</dd>
<dt>GFX7-GFX8</dt>
<dd><p class="first">The first SGPR is a 32 bit
byte offset from
<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
to per SPI base of memory
for scratch for the queue
executing the kernel
dispatch. CP obtains this
from the runtime. (The
Scratch Segment Buffer base
address is
<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
plus this offset.) The value
of Scratch Wavefront Offset must
be added to this offset by
the kernel machine code,
right shifted by 8, and
moved to the FLAT_SCRATCH_HI
SGPR register.
FLAT_SCRATCH_HI corresponds
to SGPRn-4 on GFX7, and
SGPRn-6 on GFX8 (where SGPRn
is the highest numbered SGPR
allocated to the wavefront).
FLAT_SCRATCH_HI is
multiplied by 256 (as it is
in units of 256 bytes) and
added to
<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
to calculate the per wavefront
FLAT SCRATCH BASE in flat
memory instructions that
access the scratch
apperture.</p>
<p class="last">The second SGPR is 32 bit
byte size of a single
work-item’s scratch memory
usage. CP obtains this from
the runtime, and it is
always a multiple of DWORD.
CP checks that the value in
the kernel dispatch packet
Private Segment Byte Size is
not larger, and requests the
runtime to increase the
queue’s scratch size if
necessary. The kernel code
must move it to
FLAT_SCRATCH_LO which is
SGPRn-3 on GFX7 and SGPRn-5
on GFX8. FLAT_SCRATCH_LO is
used as the FLAT SCRATCH
SIZE in flat memory
instructions. Having CP load
it once avoids loading it at
the beginning of every
wavefront.</p>
</dd>
<dt>GFX9</dt>
<dd>This is the
64 bit base address of the
per SPI scratch backing
memory managed by SPI for
the queue executing the
kernel dispatch. CP obtains
this from the runtime (and
divides it if there are
multiple Shader Arrays each
with its own SPI). The value
of Scratch Wavefront Offset must
be added by the kernel
machine code and the result
moved to the FLAT_SCRATCH
SGPR which is SGPRn-6 and
SGPRn-5. It is used as the
FLAT SCRATCH BASE in flat
memory instructions.</dd>
</dl>
</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Private Segment Size</td>
<td>1</td>
<td><p class="first">The 32 bit byte size of a
(enable_sgpr_private single
work-item’s
scratch_segment_size) memory
allocation. This is the
value from the kernel
dispatch packet Private
Segment Byte Size rounded up
by CP to a multiple of
DWORD.</p>
<p>Having CP load it once avoids
loading it at the beginning of
every wavefront.</p>
<p class="last">This is not used for
GFX7-GFX8 since it is the same
value as the second SGPR of
Flat Scratch Init. However, it
may be needed for GFX9 which
changes the meaning of the
Flat Scratch Init value.</p>
</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Grid Work-Group Count X
(enable_sgpr_grid
_workgroup_count_X)</td>
<td>1</td>
<td>32 bit count of the number of
work-groups in the X dimension
for the grid being
executed. Computed from the
fields in the kernel dispatch
packet as ((grid_size.x +
workgroup_size.x - 1) /
workgroup_size.x).</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Grid Work-Group Count Y
(enable_sgpr_grid
_workgroup_count_Y &&
less than 16 previous
SGPRs)</td>
<td>1</td>
<td><p class="first">32 bit count of the number of
work-groups in the Y dimension
for the grid being
executed. Computed from the
fields in the kernel dispatch
packet as ((grid_size.y +
workgroup_size.y - 1) /
workgroupSize.y).</p>
<p class="last">Only initialized if <16
previous SGPRs initialized.</p>
</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Grid Work-Group Count Z
(enable_sgpr_grid
_workgroup_count_Z &&
less than 16 previous
SGPRs)</td>
<td>1</td>
<td><p class="first">32 bit count of the number of
work-groups in the Z dimension
for the grid being
executed. Computed from the
fields in the kernel dispatch
packet as ((grid_size.z +
workgroup_size.z - 1) /
workgroupSize.z).</p>
<p class="last">Only initialized if <16
previous SGPRs initialized.</p>
</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Work-Group Id X
(enable_sgpr_workgroup_id
_X)</td>
<td>1</td>
<td>32 bit work-group id in X
dimension of grid for
wavefront.</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Work-Group Id Y
(enable_sgpr_workgroup_id
_Y)</td>
<td>1</td>
<td>32 bit work-group id in Y
dimension of grid for
wavefront.</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Work-Group Id Z
(enable_sgpr_workgroup_id
_Z)</td>
<td>1</td>
<td>32 bit work-group id in Z
dimension of grid for
wavefront.</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Work-Group Info
(enable_sgpr_workgroup
_info)</td>
<td>1</td>
<td>{first_wavefront, 14’b0000,
ordered_append_term[10:0],
threadgroup_size_in_wavefronts[5:0]}</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Scratch Wavefront Offset
(enable_sgpr_private
_segment_wavefront_offset)</td>
<td>1</td>
<td>32 bit byte offset from base
of scratch base of queue
executing the kernel
dispatch. Must be used as an
offset with Private
segment address when using
Scratch Segment Buffer. It
must be used to set up FLAT
SCRATCH for flat addressing
(see
<a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>).</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>The order of the VGPR registers is defined, but the compiler can specify which
ones are actually setup in the kernel descriptor using the <code class="docutils literal notranslate"><span class="pre">enable_vgpr*</span></code> bit
fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
for enabled registers are dense starting at VGPR0: the first enabled register is
VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
VGPR number.</p>
<p>VGPR register initial state is defined in
<a class="reference internal" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table"><span class="std std-ref">VGPR Register Set Up Order</span></a>.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-vgpr-register-set-up-order-table">
<caption><span class="caption-text">VGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="14%" />
<col width="36%" />
<col width="8%" />
<col width="42%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">VGPR Order</th>
<th class="head">Name
(kernel descriptor enable
field)</th>
<th class="head">Number
of
VGPRs</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>First</td>
<td>Work-Item Id X
(Always initialized)</td>
<td>1</td>
<td>32 bit work item id in X
dimension of work-group for
wavefront lane.</td>
</tr>
<tr class="row-odd"><td>then</td>
<td>Work-Item Id Y
(enable_vgpr_workitem_id
> 0)</td>
<td>1</td>
<td>32 bit work item id in Y
dimension of work-group for
wavefront lane.</td>
</tr>
<tr class="row-even"><td>then</td>
<td>Work-Item Id Z
(enable_vgpr_workitem_id
> 1)</td>
<td>1</td>
<td>32 bit work item id in Z
dimension of work-group for
wavefront lane.</td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>The setting of registers is done by GPU CP/ADC/SPI hardware as follows:</p>
<ol class="arabic simple">
<li>SGPRs before the Work-Group Ids are set by CP using the 16 User Data
registers.</li>
<li>Work-group Id registers X, Y, Z are set by ADC which supports any
combination including none.</li>
<li>Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
its value cannot included with the flat scratch init value which is per queue.</li>
<li>The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
or (X, Y, Z).</li>
</ol>
<p>Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64 bit
value to the hardware required SGPRn-3 and SGPRn-4 respectively.</p>
<p>The global segment can be accessed either using buffer instructions (GFX6 which
has V# 64 bit address support), flat instructions (GFX7-GFX9), or global
instructions (GFX9).</p>
<p>If buffer operations are used then the compiler can generate a V# with the
following properties:</p>
<ul class="simple">
<li>base address of 0</li>
<li>no swizzle</li>
<li>ATC: 1 if IOMMU present (such as APU)</li>
<li>ptr64: 1</li>
<li>MTYPE set to support memory coherence that matches the runtime (such as CC for
APU and NC for dGPU).</li>
</ul>
</div>
<div class="section" id="kernel-prolog">
<span id="amdgpu-amdhsa-kernel-prolog"></span><h4><a class="toc-backref" href="#id81">Kernel Prolog</a><a class="headerlink" href="#kernel-prolog" title="Permalink to this headline">¶</a></h4>
<div class="section" id="m0">
<span id="amdgpu-amdhsa-m0"></span><h5><a class="toc-backref" href="#id82">M0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h5>
<dl class="docutils">
<dt>GFX6-GFX8</dt>
<dd>The M0 register must be initialized with a value at least the total LDS size
if the kernel may access LDS via DS or flat operations. Total LDS size is
available in dispatch packet. For M0, it is also possible to use maximum
possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
GFX7-GFX8).</dd>
<dt>GFX9</dt>
<dd>The M0 register is not used for range checking LDS accesses and so does not
need to be initialized in the prolog.</dd>
</dl>
</div>
<div class="section" id="flat-scratch">
<span id="amdgpu-amdhsa-flat-scratch"></span><h5><a class="toc-backref" href="#id83">Flat Scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h5>
<p>If the kernel may use flat operations to access scratch memory, the prolog code
must set up FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which
are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wavefront
Offset SGPR registers (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>):</p>
<dl class="docutils">
<dt>GFX6</dt>
<dd>Flat scratch is not supported.</dd>
<dt>GFX7-GFX8</dt>
<dd><ol class="first last arabic simple">
<li>The low word of Flat Scratch Init is 32 bit byte offset from
<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code> to the base of scratch backing memory
being managed by SPI for the queue executing the kernel dispatch. This is
the same value used in the Scratch Segment Buffer V# base address. The
prolog must add the value of Scratch Wavefront Offset to get the wavefront’s byte
scratch backing memory offset from <code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>. Since
FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted
by 8 before moving into FLAT_SCRATCH_LO.</li>
<li>The second word of Flat Scratch Init is 32 bit byte size of a single
work-items scratch memory usage. This is directly loaded from the kernel
dispatch packet Private Segment Byte Size and rounded up to a multiple of
DWORD. Having CP load it once avoids loading it at the beginning of every
wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT SCRATCH
SIZE.</li>
</ol>
</dd>
<dt>GFX9</dt>
<dd>The Flat Scratch Init is the 64 bit address of the base of scratch backing
memory being managed by SPI for the queue executing the kernel dispatch. The
prolog must add the value of Scratch Wavefront Offset and moved to the FLAT_SCRATCH
pair for use as the flat scratch base in flat memory instructions.</dd>
</dl>
</div>
</div>
<div class="section" id="memory-model">
<span id="amdgpu-amdhsa-memory-model"></span><h4><a class="toc-backref" href="#id84">Memory Model</a><a class="headerlink" href="#memory-model" title="Permalink to this headline">¶</a></h4>
<p>This section describes the mapping of LLVM memory model onto AMDGPU machine code
(see <a class="reference internal" href="LangRef.html#memmodel"><span class="std std-ref">Memory Model for Concurrent Operations</span></a>). <em>The implementation is WIP.</em></p>
<p>The AMDGPU backend supports the memory synchronization scopes specified in
<a class="reference internal" href="#amdgpu-memory-scopes"><span class="std std-ref">Memory Scopes</span></a>.</p>
<p>The code sequences used to implement the memory model are defined in table
<a class="reference internal" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table"><span class="std std-ref">AMDHSA Memory Model Code Sequences GFX6-GFX9</span></a>.</p>
<p>The sequences specify the order of instructions that a single thread must
execute. The <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> and <code class="docutils literal notranslate"><span class="pre">buffer_wbinvl1_vol</span></code> are defined with respect
to other memory instructions executed by the same thread. This allows them to be
moved earlier or later which can allow them to be combined with other instances
of the same instruction, or hoisted/sunk out of loops to improve
performance. Only the instructions related to the memory model are given;
additional <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions are required to ensure registers are
defined before being used. These may be able to be combined with the memory
model <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions as described above.</p>
<p>The AMDGPU backend supports the following memory models:</p>
<blockquote>
<div><dl class="docutils">
<dt>HSA Memory Model <a class="reference internal" href="#hsa" id="id34">[HSA]</a></dt>
<dd>The HSA memory model uses a single happens-before relation for all address
spaces (see <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a>).</dd>
<dt>OpenCL Memory Model <a class="reference internal" href="#id45" id="id35">[OpenCL]</a></dt>
<dd>The OpenCL memory model which has separate happens-before relations for the
global and local address spaces. Only a fence specifying both global and
local address space, and seq_cst instructions join the relationships. Since
the LLVM <code class="docutils literal notranslate"><span class="pre">memfence</span></code> instruction does not allow an address space to be
specified the OpenCL fence has to convervatively assume both local and
global address space was specified. However, optimizations can often be
done to eliminate the additional <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions when there are
no intervening memory instructions which access the corresponding address
space. The code sequences in the table indicate what can be omitted for the
OpenCL memory. The target triple environment is used to determine if the
source language is OpenCL (see <a class="reference internal" href="#amdgpu-opencl"><span class="std std-ref">OpenCL</span></a>).</dd>
</dl>
</div></blockquote>
<p><code class="docutils literal notranslate"><span class="pre">ds/flat_load/store/atomic</span></code> instructions to local memory are termed LDS
operations.</p>
<p><code class="docutils literal notranslate"><span class="pre">buffer/global/flat_load/store/atomic</span></code> instructions to global memory are
termed vector memory operations.</p>
<p>For GFX6-GFX9:</p>
<ul class="simple">
<li>Each agent has multiple compute units (CU).</li>
<li>Each CU has multiple SIMDs that execute wavefronts.</li>
<li>The wavefronts for a single work-group are executed in the same CU but may be
executed by different SIMDs.</li>
<li>Each CU has a single LDS memory shared by the wavefronts of the work-groups
executing on it.</li>
<li>All LDS operations of a CU are performed as wavefront wide operations in a
global order and involve no caching. Completion is reported to a wavefront in
execution order.</li>
<li>The LDS memory has multiple request queues shared by the SIMDs of a
CU. Therefore, the LDS operations performed by different wavefronts of a work-group
can be reordered relative to each other, which can result in reordering the
visibility of vector memory operations with respect to LDS operations of other
wavefronts in the same work-group. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">lgkmcnt(0)</span></code> is required to
ensure synchronization between LDS operations and vector memory operations
between wavefronts of a work-group, but not between operations performed by the
same wavefront.</li>
<li>The vector memory operations are performed as wavefront wide operations and
completion is reported to a wavefront in execution order. The exception is
that for GFX7-GFX9 <code class="docutils literal notranslate"><span class="pre">flat_load/store/atomic</span></code> instructions can report out of
vector memory order if they access LDS memory, and out of LDS operation order
if they access global memory.</li>
<li>The vector memory operations access a single vector L1 cache shared by all
SIMDs a CU. Therefore, no special action is required for coherence between the
lanes of a single wavefront, or for coherence between wavefronts in the same
work-group. A <code class="docutils literal notranslate"><span class="pre">buffer_wbinvl1_vol</span></code> is required for coherence between wavefronts
executing in different work-groups as they may be executing on different CUs.</li>
<li>The scalar memory operations access a scalar L1 cache shared by all wavefronts
on a group of CUs. The scalar and vector L1 caches are not coherent. However,
scalar operations are used in a restricted way so do not impact the memory
model. See <a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</li>
<li>The vector and scalar memory operations use an L2 cache shared by all CUs on
the same agent.</li>
<li>The L2 cache has independent channels to service disjoint ranges of virtual
addresses.</li>
<li>Each CU has a separate request queue per channel. Therefore, the vector and
scalar memory operations performed by wavefronts executing in different work-groups
(which may be executing on different CUs) of an agent can be reordered
relative to each other. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">vmcnt(0)</span></code> is required to ensure
synchronization between vector memory operations of different CUs. It ensures a
previous vector memory operation has completed before executing a subsequent
vector memory or LDS operation and so can be used to meet the requirements of
acquire and release.</li>
<li>The L2 cache can be kept coherent with other agents on some targets, or ranges
of virtual addresses can be set up to bypass it to ensure system coherence.</li>
</ul>
<p>Private address space uses <code class="docutils literal notranslate"><span class="pre">buffer_load/store</span></code> using the scratch V# (GFX6-GFX8),
or <code class="docutils literal notranslate"><span class="pre">scratch_load/store</span></code> (GFX9). Since only a single thread is accessing the
memory, atomic memory orderings are not meaningful and all accesses are treated
as non-atomic.</p>
<p>Constant address space uses <code class="docutils literal notranslate"><span class="pre">buffer/global_load</span></code> instructions (or equivalent
scalar memory instructions). Since the constant address space contents do not
change during the execution of a kernel dispatch it is not legal to perform
stores, and atomic memory orderings are not meaningful and all access are
treated as non-atomic.</p>
<p>A memory synchronization scope wider than work-group is not meaningful for the
group (LDS) address space and is treated as work-group.</p>
<p>The memory model does not support the region address space which is treated as
non-atomic.</p>
<p>Acquire memory ordering is not meaningful on store atomic instructions and is
treated as non-atomic.</p>
<p>Release memory ordering is not meaningful on load atomic instructions and is
treated a non-atomic.</p>
<p>Acquire-release memory ordering is not meaningful on load or store atomic
instructions and is treated as acquire and release respectively.</p>
<p>AMDGPU backend only uses scalar memory operations to access memory that is
proven to not change during the execution of the kernel dispatch. This includes
constant address space and global address space for program scope const
variables. Therefore the kernel machine code does not have to maintain the
scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar
and vector L1 caches are invalidated between kernel dispatches by CP since
constant address space data may change between kernel dispatch executions. See
<a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</p>
<p>The one execption is if scalar writes are used to spill SGPR registers. In this
case the AMDGPU backend ensures the memory location used to spill is never
accessed by vector memory operations at the same time. If scalar writes are used
then a <code class="docutils literal notranslate"><span class="pre">s_dcache_wb</span></code> is inserted before the <code class="docutils literal notranslate"><span class="pre">s_endpgm</span></code> and before a function
return since the locations may be used for vector memory instructions by a
future wavefront that uses the same scratch area, or a function call that creates a
frame at the same address, respectively. There is no need for a <code class="docutils literal notranslate"><span class="pre">s_dcache_inv</span></code>
as all scalar writes are write-before-read in the same thread.</p>
<p>Scratch backing memory (which is used for the private address space)
is accessed with MTYPE NC_NV (non-coherenent non-volatile). Since the private
address space is only accessed by a single thread, and is always
write-before-read, there is never a need to invalidate these entries from the L1
cache. Hence all cache invalidates are done as <code class="docutils literal notranslate"><span class="pre">*_vol</span></code> to only invalidate the
volatile cache lines.</p>
<p>On dGPU the kernarg backing memory is accessed as UC (uncached) to avoid needing
to invalidate the L2 cache. This also causes it to be treated as
non-volatile and so is not invalidated by <code class="docutils literal notranslate"><span class="pre">*_vol</span></code>. On APU it is accessed as CC
(cache coherent) and so the L2 cache will coherent with the CPU and other
agents.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table">
<caption><span class="caption-text">AMDHSA Memory Model Code Sequences GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="15%" />
<col width="15%" />
<col width="18%" />
<col width="13%" />
<col width="39%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">LLVM Instr</th>
<th class="head">LLVM Memory
Ordering</th>
<th class="head">LLVM Memory
Sync Scope</th>
<th class="head">AMDGPU
Address
Space</th>
<th class="head">AMDGPU Machine Code</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td colspan="5"><strong>Non-Atomic</strong></td>
</tr>
<tr class="row-odd"><td>load</td>
<td><em>none</em></td>
<td><em>none</em></td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
<li>private</li>
<li>constant</li>
</ul>
</td>
<td><ul class="first last simple">
<li>!volatile & !nontemporal<ol class="arabic">
<li>buffer/global/flat_load</li>
</ol>
</li>
<li>volatile & !nontemporal<ol class="arabic">
<li>buffer/global/flat_load
glc=1</li>
</ol>
</li>
<li>nontemporal<ol class="arabic">
<li>buffer/global/flat_load
glc=1 slc=1</li>
</ol>
</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>load</td>
<td><em>none</em></td>
<td><em>none</em></td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_load</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>store</td>
<td><em>none</em></td>
<td><em>none</em></td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
<li>private</li>
<li>constant</li>
</ul>
</td>
<td><ul class="first last simple">
<li>!nontemporal<ol class="arabic">
<li>buffer/global/flat_store</li>
</ol>
</li>
<li>nontemporal<ol class="arabic">
<li>buffer/global/flat_stote
glc=1 slc=1</li>
</ol>
</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>store</td>
<td><em>none</em></td>
<td><em>none</em></td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_store</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td colspan="5"><strong>Unordered Atomic</strong></td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>unordered</td>
<td><em>any</em></td>
<td><em>any</em></td>
<td><em>Same as non-atomic</em>.</td>
</tr>
<tr class="row-odd"><td>store atomic</td>
<td>unordered</td>
<td><em>any</em></td>
<td><em>any</em></td>
<td><em>Same as non-atomic</em>.</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>unordered</td>
<td><em>any</em></td>
<td><em>any</em></td>
<td><em>Same as monotonic
atomic</em>.</td>
</tr>
<tr class="row-odd"><td colspan="5"><strong>Monotonic Atomic</strong></td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/flat_load</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>load atomic</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_load</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/flat_load
glc=1</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>store atomic</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/flat_store</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>store atomic</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_store</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>monotonic</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_atomic</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td colspan="5"><strong>Acquire Atomic</strong></td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/ds/flat_load</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>load atomic</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/flat_load</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>ds_load</li>
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the load
atomic value being
acquired.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td>load atomic</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>flat_load</li>
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the load
atomic value being
acquired.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>buffer/global/flat_load
glc=1</li>
<li>s_waitcnt vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>Must happen before
following
buffer_wbinvl1_vol.</li>
<li>Ensures the load
has completed
before invalidating
the cache.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="3">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/atomicrmw.</li>
<li>Ensures that
following
loads will not see
stale global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td>load atomic</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>flat_load glc=1</li>
<li>s_waitcnt vmcnt(0) &
lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL omit
lgkmcnt(0).</li>
<li>Must happen before
following
buffer_wbinvl1_vol.</li>
<li>Ensures the flat_load
has completed
before invalidating
the cache.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="3">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/ds/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>ds_atomic</li>
<li>waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the
atomicrmw value
being acquired.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>flat_atomic</li>
<li>waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the
atomicrmw value
being acquired.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>buffer/global/flat_atomic</li>
<li>s_waitcnt vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>Must happen before
following
buffer_wbinvl1_vol.</li>
<li>Ensures the
atomicrmw has
completed before
invalidating the
cache.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="3">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>flat_atomic</li>
<li>s_waitcnt vmcnt(0) &
lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit
lgkmcnt(0).</li>
<li>Must happen before
following
buffer_wbinvl1_vol.</li>
<li>Ensures the
atomicrmw has
completed before
invalidating the
cache.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="3">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>fence</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><em>none</em></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td>fence</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><em>none</em></td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL and
address space is
not generic, omit.</li>
<li>However, since LLVM
currently has no
address space on
the fence need to
conservatively
always generate. If
fence had an
address space then
set to address
space of OpenCL
fence flag, or to
generic if both
local and global
flags are
specified.</li>
<li>Must happen after
any preceding
local/generic load
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
fence-paired-atomic).</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the
value read by the
fence-paired-atomic.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>fence</td>
<td>acquire</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><em>none</em></td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL and
address space is
not generic, omit
lgkmcnt(0).</li>
<li>However, since LLVM
currently has no
address space on
the fence need to
conservatively
always generate
(see comment for
previous fence).</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic load
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
fence-paired-atomic).</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic load
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
fence-paired-atomic).</li>
<li>Must happen before
the following
buffer_wbinvl1_vol.</li>
<li>Ensures that the
fence-paired atomic
has completed
before invalidating
the
cache. Therefore
any following
locations read must
be no older than
the value read by
the
fence-paired-atomic.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="2">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before any
following global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td colspan="5"><strong>Release Atomic</strong></td>
</tr>
<tr class="row-even"><td>store atomic</td>
<td>release</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/ds/flat_store</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>store atomic</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
store.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
store that is being
released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>buffer/global/flat_store</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>store atomic</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_store</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>store atomic</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
store.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
store that is being
released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>flat_store</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>store atomic</td>
<td>release</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit
lgkmcnt(0).</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
store.</li>
<li>Ensures that all
memory operations
to memory have
completed before
performing the
store that is being
released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>buffer/global/ds/flat_store</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>release</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/ds/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
atomicrmw that is
being released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>buffer/global/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>ds_atomic</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
atomicrmw that is
being released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>release</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit
lgkmcnt(0).</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to global and local
have completed
before performing
the atomicrmw that
is being released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>buffer/global/ds/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>fence</td>
<td>release</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><em>none</em></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td>fence</td>
<td>release</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><em>none</em></td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL and
address space is
not generic, omit.</li>
<li>However, since LLVM
currently has no
address space on
the fence need to
conservatively
always generate. If
fence had an
address space then
set to address
space of OpenCL
fence flag, or to
generic if both
local and global
flags are
specified.</li>
<li>Must happen after
any preceding
local/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Must happen before
any following store
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
fence-paired-atomic).</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
following
fence-paired-atomic.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>fence</td>
<td>release</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><em>none</em></td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL and
address space is
not generic, omit
lgkmcnt(0).</li>
<li>If OpenCL and
address space is
local, omit
vmcnt(0).</li>
<li>However, since LLVM
currently has no
address space on
the fence need to
conservatively
always generate. If
fence had an
address space then
set to address
space of OpenCL
fence flag, or to
generic if both
local and global
flags are
specified.</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
any following store
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
fence-paired-atomic).</li>
<li>Ensures that all
memory operations
have
completed before
performing the
following
fence-paired-atomic.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td colspan="5"><strong>Acquire-Release Atomic</strong></td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first last arabic simple">
<li>buffer/global/ds/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
atomicrmw that is
being released.</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li>buffer/global/flat_atomic</li>
</ol>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>ds_atomic</li>
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the load
atomic value being
acquired.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing the
atomicrmw that is
being released.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="2">
<li>flat_atomic</li>
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL, omit.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures any
following global
data read is no
older than the load
atomic value being
acquired.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit
lgkmcnt(0).</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to global have
completed before
performing the
atomicrmw that is
being released.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="2">
<li>buffer/global/flat_atomic</li>
<li>s_waitcnt vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>Must happen before
following
buffer_wbinvl1_vol.</li>
<li>Ensures the
atomicrmw has
completed before
invalidating the
cache.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="4">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit
lgkmcnt(0).</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
atomicrmw.</li>
<li>Ensures that all
memory operations
to global have
completed before
performing the
atomicrmw that is
being released.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="2">
<li>flat_atomic</li>
<li>s_waitcnt vmcnt(0) &
lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL, omit
lgkmcnt(0).</li>
<li>Must happen before
following
buffer_wbinvl1_vol.</li>
<li>Ensures the
atomicrmw has
completed before
invalidating the
cache.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="4">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>fence</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><em>none</em></td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td>fence</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><em>none</em></td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>If OpenCL and
address space is
not generic, omit.</li>
<li>However,
since LLVM
currently has no
address space on
the fence need to
conservatively
always generate
(see comment for
previous fence).</li>
<li>Must happen after
any preceding
local/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures that all
memory operations
to local have
completed before
performing any
following global
memory operations.</li>
<li>Ensures that the
preceding
local/generic load
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
acquire-fence-paired-atomic
) has completed
before following
global memory
operations. This
satisfies the
requirements of
acquire.</li>
<li>Ensures that all
previous memory
operations have
completed before a
following
local/generic store
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
release-fence-paired-atomic
). This satisfies the
requirements of
release.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-even"><td>fence</td>
<td>acq_rel</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><em>none</em></td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>If OpenCL and
address space is
not generic, omit
lgkmcnt(0).</li>
<li>However, since LLVM
currently has no
address space on
the fence need to
conservatively
always generate
(see comment for
previous fence).</li>
<li>Could be split into
separate s_waitcnt
vmcnt(0) and
s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>s_waitcnt vmcnt(0)
must happen after
any preceding
global/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>s_waitcnt lgkmcnt(0)
must happen after
any preceding
local/generic
load/store/load
atomic/store
atomic/atomicrmw.</li>
<li>Must happen before
the following
buffer_wbinvl1_vol.</li>
<li>Ensures that the
preceding
global/local/generic
load
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
acquire-fence-paired-atomic
) has completed
before invalidating
the cache. This
satisfies the
requirements of
acquire.</li>
<li>Ensures that all
previous memory
operations have
completed before a
following
global/local/generic
store
atomic/atomicrmw
with an equal or
wider sync scope
and memory ordering
stronger than
unordered (this is
termed the
release-fence-paired-atomic
). This satisfies the
requirements of
release.</li>
</ul>
</div></blockquote>
<ol class="arabic simple" start="2">
<li>buffer_wbinvl1_vol</li>
</ol>
<blockquote class="last">
<div><ul class="simple">
<li>Must happen before
any following
global/generic
load/load
atomic/store/store
atomic/atomicrmw.</li>
<li>Ensures that
following loads
will not see stale
global data. This
satisfies the
requirements of
acquire.</li>
</ul>
</div></blockquote>
</td>
</tr>
<tr class="row-odd"><td colspan="5"><strong>Sequential Consistent Atomic</strong></td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><em>Same as corresponding
load atomic acquire,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
<tr class="row-odd"><td>load atomic</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>Must
happen after
preceding
global/generic load
atomic/store
atomic/atomicrmw
with memory
ordering of seq_cst
and with equal or
wider sync scope.
(Note that seq_cst
fences have their
own s_waitcnt
lgkmcnt(0) and so do
not need to be
considered.)</li>
<li>Ensures any
preceding
sequential
consistent local
memory instructions
have completed
before executing
this sequentially
consistent
instruction. This
prevents reordering
a seq_cst store
followed by a
seq_cst load. (Note
that seq_cst is
stronger than
acquire/release as
the reordering of
load acquire
followed by a store
release is
prevented by the
waitcnt of
the release, but
there is nothing
preventing a store
release followed by
load acquire from
competing out of
order.)</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li><em>Following
instructions same as
corresponding load
atomic acquire,
except must generated
all instructions even
for OpenCL.</em></li>
</ol>
</td>
</tr>
<tr class="row-even"><td>load atomic</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>local</li>
</ul>
</td>
<td><em>Same as corresponding
load atomic acquire,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
<tr class="row-odd"><td>load atomic</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><ol class="first arabic simple">
<li>s_waitcnt lgkmcnt(0) &
vmcnt(0)</li>
</ol>
<blockquote>
<div><ul class="simple">
<li>Could be split into
separate s_waitcnt
vmcnt(0)
and s_waitcnt
lgkmcnt(0) to allow
them to be
independently moved
according to the
following rules.</li>
<li>waitcnt lgkmcnt(0)
must happen after
preceding
global/generic load
atomic/store
atomic/atomicrmw
with memory
ordering of seq_cst
and with equal or
wider sync scope.
(Note that seq_cst
fences have their
own s_waitcnt
lgkmcnt(0) and so do
not need to be
considered.)</li>
<li>waitcnt vmcnt(0)
must happen after
preceding
global/generic load
atomic/store
atomic/atomicrmw
with memory
ordering of seq_cst
and with equal or
wider sync scope.
(Note that seq_cst
fences have their
own s_waitcnt
vmcnt(0) and so do
not need to be
considered.)</li>
<li>Ensures any
preceding
sequential
consistent global
memory instructions
have completed
before executing
this sequentially
consistent
instruction. This
prevents reordering
a seq_cst store
followed by a
seq_cst load. (Note
that seq_cst is
stronger than
acquire/release as
the reordering of
load acquire
followed by a store
release is
prevented by the
waitcnt of
the release, but
there is nothing
preventing a store
release followed by
load acquire from
competing out of
order.)</li>
</ul>
</div></blockquote>
<ol class="last arabic simple" start="2">
<li><em>Following
instructions same as
corresponding load
atomic acquire,
except must generated
all instructions even
for OpenCL.</em></li>
</ol>
</td>
</tr>
<tr class="row-even"><td>store atomic</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><em>Same as corresponding
store atomic release,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
<tr class="row-odd"><td>store atomic</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><em>Same as corresponding
store atomic release,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
<tr class="row-even"><td>atomicrmw</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>local</li>
<li>generic</li>
</ul>
</td>
<td><em>Same as corresponding
atomicrmw acq_rel,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
<tr class="row-odd"><td>atomicrmw</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><ul class="first last simple">
<li>global</li>
<li>generic</li>
</ul>
</td>
<td><em>Same as corresponding
atomicrmw acq_rel,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
<tr class="row-even"><td>fence</td>
<td>seq_cst</td>
<td><ul class="first last simple">
<li>singlethread</li>
<li>wavefront</li>
<li>workgroup</li>
<li>agent</li>
<li>system</li>
</ul>
</td>
<td><em>none</em></td>
<td><em>Same as corresponding
fence acq_rel,
except must generated
all instructions even
for OpenCL.</em></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>The memory order also adds the single thread optimization constrains defined in
table
<a class="reference internal" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table"><span class="std std-ref">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9</span></a>.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table">
<caption><span class="caption-text">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="16%" />
<col width="84%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">LLVM Memory</th>
<th class="head">Optimization Constraints</th>
</tr>
<tr class="row-even"><th class="head">Ordering</th>
<th class="head"> </th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-odd"><td>unordered</td>
<td><em>none</em></td>
</tr>
<tr class="row-even"><td>monotonic</td>
<td><em>none</em></td>
</tr>
<tr class="row-odd"><td>acquire</td>
<td><ul class="first last simple">
<li>If a load atomic/atomicrmw then no following load/load
atomic/store/ store atomic/atomicrmw/fence instruction can
be moved before the acquire.</li>
<li>If a fence then same as load atomic, plus no preceding
associated fence-paired-atomic can be moved after the fence.</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>release</td>
<td><ul class="first last simple">
<li>If a store atomic/atomicrmw then no preceding load/load
atomic/store/ store atomic/atomicrmw/fence instruction can
be moved after the release.</li>
<li>If a fence then same as store atomic, plus no following
associated fence-paired-atomic can be moved before the
fence.</li>
</ul>
</td>
</tr>
<tr class="row-odd"><td>acq_rel</td>
<td>Same constraints as both acquire and release.</td>
</tr>
<tr class="row-even"><td>seq_cst</td>
<td><ul class="first last simple">
<li>If a load atomic then same constraints as acquire, plus no
preceding sequentially consistent load atomic/store
atomic/atomicrmw/fence instruction can be moved after the
seq_cst.</li>
<li>If a store atomic then the same constraints as release, plus
no following sequentially consistent load atomic/store
atomic/atomicrmw/fence instruction can be moved before the
seq_cst.</li>
<li>If an atomicrmw/fence then same constraints as acq_rel.</li>
</ul>
</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="trap-handler-abi">
<h4><a class="toc-backref" href="#id85">Trap Handler ABI</a><a class="headerlink" href="#trap-handler-abi" title="Permalink to this headline">¶</a></h4>
<p>For code objects generated by AMDGPU backend for HSA <a class="reference internal" href="#hsa" id="id36">[HSA]</a> compatible runtimes
(such as ROCm <a class="reference internal" href="#amd-rocm" id="id37">[AMD-ROCm]</a>), the runtime installs a trap handler that supports
the <code class="docutils literal notranslate"><span class="pre">s_trap</span></code> instruction with the following usage:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-amdhsa-os-table">
<caption><span class="caption-text">AMDGPU Trap Handler for AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="26%" />
<col width="21%" />
<col width="21%" />
<col width="32%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Usage</th>
<th class="head">Code Sequence</th>
<th class="head">Trap Handler
Inputs</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x00</span></code></td>
<td> </td>
<td>Reserved by hardware.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">debugtrap(arg)</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x01</span></code></td>
<td><dl class="first last docutils">
<dt><code class="docutils literal notranslate"><span class="pre">SGPR0-1</span></code>:</dt>
<dd><code class="docutils literal notranslate"><span class="pre">queue_ptr</span></code></dd>
<dt><code class="docutils literal notranslate"><span class="pre">VGPR0</span></code>:</dt>
<dd><code class="docutils literal notranslate"><span class="pre">arg</span></code></dd>
</dl>
</td>
<td>Reserved for HSA
<code class="docutils literal notranslate"><span class="pre">debugtrap</span></code>
intrinsic (not
implemented).</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">llvm.trap</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x02</span></code></td>
<td><dl class="first last docutils">
<dt><code class="docutils literal notranslate"><span class="pre">SGPR0-1</span></code>:</dt>
<dd><code class="docutils literal notranslate"><span class="pre">queue_ptr</span></code></dd>
</dl>
</td>
<td>Causes dispatch to be
terminated and its
associated queue put
into the error state.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">llvm.debugtrap</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x03</span></code></td>
<td> </td>
<td><ul class="first last simple">
<li>If debugger not
installed then
behaves as a
no-operation. The
trap handler is
entered and
immediately returns
to continue
execution of the
wavefront.</li>
<li>If the debugger is
installed, causes
the debug trap to be
reported by the
debugger and the
wavefront is put in
the halt state until
resumed by the
debugger.</li>
</ul>
</td>
</tr>
<tr class="row-even"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x04</span></code></td>
<td> </td>
<td>Reserved.</td>
</tr>
<tr class="row-odd"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x05</span></code></td>
<td> </td>
<td>Reserved.</td>
</tr>
<tr class="row-even"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x06</span></code></td>
<td> </td>
<td>Reserved.</td>
</tr>
<tr class="row-odd"><td>debugger breakpoint</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x07</span></code></td>
<td> </td>
<td>Reserved for debugger
breakpoints.</td>
</tr>
<tr class="row-even"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x08</span></code></td>
<td> </td>
<td>Reserved.</td>
</tr>
<tr class="row-odd"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0xfe</span></code></td>
<td> </td>
<td>Reserved.</td>
</tr>
<tr class="row-even"><td>reserved</td>
<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0xff</span></code></td>
<td> </td>
<td>Reserved.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
<div class="section" id="amdpal">
<h3><a class="toc-backref" href="#id86">AMDPAL</a><a class="headerlink" href="#amdpal" title="Permalink to this headline">¶</a></h3>
<p>This section provides code conventions used when the target triple OS is
<code class="docutils literal notranslate"><span class="pre">amdpal</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>) for passing runtime parameters
from the application/runtime to each invocation of a hardware shader. These
parameters include both generic, application-controlled parameters called
<em>user data</em> as well as system-generated parameters that are a product of the
draw or dispatch execution.</p>
<div class="section" id="user-data">
<h4><a class="toc-backref" href="#id87">User Data</a><a class="headerlink" href="#user-data" title="Permalink to this headline">¶</a></h4>
<p>Each hardware stage has a set of 32-bit <em>user data registers</em> which can be
written from a command buffer and then loaded into SGPRs when waves are launched
via a subsequent dispatch or draw operation. This is the way most arguments are
passed from the application/runtime to a hardware shader.</p>
</div>
<div class="section" id="compute-user-data">
<h4><a class="toc-backref" href="#id88">Compute User Data</a><a class="headerlink" href="#compute-user-data" title="Permalink to this headline">¶</a></h4>
<p>Compute shader user data mappings are simpler than graphics shaders, and have a
fixed mapping.</p>
<p>Note that there are always 10 available <em>user data entries</em> in registers -
entries beyond that limit must be fetched from memory (via the spill table
pointer) by the shader.</p>
<blockquote>
<div><table border="1" class="docutils" id="pal-compute-user-data-registers">
<caption><span class="caption-text">PAL Compute Shader User Data Registers</span><a class="headerlink" href="#pal-compute-user-data-registers" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="20%" />
<col width="80%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">User Register</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>0</td>
<td>Global Internal Table (32-bit pointer)</td>
</tr>
<tr class="row-odd"><td>1</td>
<td>Per-Shader Internal Table (32-bit pointer)</td>
</tr>
<tr class="row-even"><td>2 - 11</td>
<td>Application-Controlled User Data (10 32-bit values)</td>
</tr>
<tr class="row-odd"><td>12</td>
<td>Spill Table (32-bit pointer)</td>
</tr>
<tr class="row-even"><td>13 - 14</td>
<td>Thread Group Count (64-bit pointer)</td>
</tr>
<tr class="row-odd"><td>15</td>
<td>GDS Range</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="graphics-user-data">
<h4><a class="toc-backref" href="#id89">Graphics User Data</a><a class="headerlink" href="#graphics-user-data" title="Permalink to this headline">¶</a></h4>
<p>Graphics pipelines support a much more flexible user data mapping:</p>
<blockquote>
<div><table border="1" class="docutils" id="pal-graphics-user-data-registers">
<caption><span class="caption-text">PAL Graphics Shader User Data Registers</span><a class="headerlink" href="#pal-graphics-user-data-registers" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="23%" />
<col width="77%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">User Register</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>0</td>
<td>Global Internal Table (32-bit pointer)</td>
</tr>
<tr class="row-odd"><td><ul class="first last simple">
<li></li>
</ul>
</td>
<td>Per-Shader Internal Table (32-bit pointer)</td>
</tr>
<tr class="row-even"><td><ul class="first last simple">
<li>1-15</li>
</ul>
</td>
<td>Application Controlled User Data
(1-15 Contiguous 32-bit Values in Registers)</td>
</tr>
<tr class="row-odd"><td><ul class="first last simple">
<li></li>
</ul>
</td>
<td>Spill Table (32-bit pointer)</td>
</tr>
<tr class="row-even"><td><ul class="first last simple">
<li></li>
</ul>
</td>
<td>Draw Index (First Stage Only)</td>
</tr>
<tr class="row-odd"><td><ul class="first last simple">
<li></li>
</ul>
</td>
<td>Vertex Offset (First Stage Only)</td>
</tr>
<tr class="row-even"><td><ul class="first last simple">
<li></li>
</ul>
</td>
<td>Instance Offset (First Stage Only)</td>
</tr>
</tbody>
</table>
<p>The placement of the global internal table remains fixed in the first <em>user
data SGPR register</em>. Otherwise all parameters are optional, and can be mapped
to any desired <em>user data SGPR register</em>, with the following regstrictions:</p>
<ul class="simple">
<li>Draw Index, Vertex Offset, and Instance Offset can only be used by the first
activehardware stage in a graphics pipeline (i.e. where the API vertex
shader runs).</li>
<li>Application-controlled user data must be mapped into a contiguous range of
user data registers.</li>
<li>The application-controlled user data range supports compaction remapping, so
only <em>entries</em> that are actually consumed by the shader must be assigned to
corresponding <em>registers</em>. Note that in order to support an efficient runtime
implementation, the remapping must pack <em>registers</em> in the same order as
<em>entries</em>, with unused <em>entries</em> removed.</li>
</ul>
</div></blockquote>
</div>
<div class="section" id="global-internal-table">
<span id="pal-global-internal-table"></span><h4><a class="toc-backref" href="#id90">Global Internal Table</a><a class="headerlink" href="#global-internal-table" title="Permalink to this headline">¶</a></h4>
<p>The global internal table is a table of <em>shader resource descriptors</em> (SRDs) that
define how certain engine-wide, runtime-managed resources should be accessed
from a shader. The majority of these resources have HW-defined formats, and it
is up to the compiler to write/read data as required by the target hardware.</p>
<p>The following table illustrates the required format:</p>
<blockquote>
<div><table border="1" class="docutils" id="pal-git-table">
<caption><span class="caption-text">PAL Global Internal Table</span><a class="headerlink" href="#pal-git-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="25%" />
<col width="75%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Offset</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>0-3</td>
<td>Graphics Scratch SRD</td>
</tr>
<tr class="row-odd"><td>4-7</td>
<td>Compute Scratch SRD</td>
</tr>
<tr class="row-even"><td>8-11</td>
<td>ES/GS Ring Output SRD</td>
</tr>
<tr class="row-odd"><td>12-15</td>
<td>ES/GS Ring Input SRD</td>
</tr>
<tr class="row-even"><td>16-19</td>
<td>GS/VS Ring Output #0</td>
</tr>
<tr class="row-odd"><td>20-23</td>
<td>GS/VS Ring Output #1</td>
</tr>
<tr class="row-even"><td>24-27</td>
<td>GS/VS Ring Output #2</td>
</tr>
<tr class="row-odd"><td>28-31</td>
<td>GS/VS Ring Output #3</td>
</tr>
<tr class="row-even"><td>32-35</td>
<td>GS/VS Ring Input SRD</td>
</tr>
<tr class="row-odd"><td>36-39</td>
<td>Tessellation Factor Buffer SRD</td>
</tr>
<tr class="row-even"><td>40-43</td>
<td>Off-Chip LDS Buffer SRD</td>
</tr>
<tr class="row-odd"><td>44-47</td>
<td>Off-Chip Param Cache Buffer SRD</td>
</tr>
<tr class="row-even"><td>48-51</td>
<td>Sample Position Buffer SRD</td>
</tr>
<tr class="row-odd"><td>52</td>
<td>vaRange::ShadowDescriptorTable High Bits</td>
</tr>
</tbody>
</table>
<p>The pointer to the global internal table passed to the shader as user data
is a 32-bit pointer. The top 32 bits should be assumed to be the same as
the top 32 bits of the pipeline, so the shader may use the program
counter’s top 32 bits.</p>
</div></blockquote>
</div>
</div>
<div class="section" id="unspecified-os">
<h3><a class="toc-backref" href="#id91">Unspecified OS</a><a class="headerlink" href="#unspecified-os" title="Permalink to this headline">¶</a></h3>
<p>This section provides code conventions used when the target triple OS is
empty (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
<div class="section" id="id38">
<h4><a class="toc-backref" href="#id92">Trap Handler ABI</a><a class="headerlink" href="#id38" title="Permalink to this headline">¶</a></h4>
<p>For code objects generated by AMDGPU backend for non-amdhsa OS, the runtime does
not install a trap handler. The <code class="docutils literal notranslate"><span class="pre">llvm.trap</span></code> and <code class="docutils literal notranslate"><span class="pre">llvm.debugtrap</span></code>
instructions are handled as follows:</p>
<blockquote>
<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-non-amdhsa-os-table">
<caption><span class="caption-text">AMDGPU Trap Handler for Non-AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-non-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="21%" />
<col width="21%" />
<col width="59%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Usage</th>
<th class="head">Code Sequence</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>llvm.trap</td>
<td>s_endpgm</td>
<td>Causes wavefront to be terminated.</td>
</tr>
<tr class="row-odd"><td>llvm.debugtrap</td>
<td><em>none</em></td>
<td>Compiler warning given that there is no
trap handler installed.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
</div>
</div>
<div class="section" id="source-languages">
<h2><a class="toc-backref" href="#id93">Source Languages</a><a class="headerlink" href="#source-languages" title="Permalink to this headline">¶</a></h2>
<div class="section" id="opencl">
<span id="amdgpu-opencl"></span><h3><a class="toc-backref" href="#id94">OpenCL</a><a class="headerlink" href="#opencl" title="Permalink to this headline">¶</a></h3>
<p>When the language is OpenCL the following differences occur:</p>
<ol class="arabic simple">
<li>The OpenCL memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
<li>The AMDGPU backend appends additional arguments to the kernel’s explicit
arguments for the AMDHSA OS (see
<a class="reference internal" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table"><span class="std std-ref">OpenCL kernel implicit arguments appended for AMDHSA OS</span></a>).</li>
<li>Additional metadata is generated
(see <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>).</li>
</ol>
<blockquote>
<div><table border="1" class="docutils" id="opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table">
<caption><span class="caption-text">OpenCL kernel implicit arguments appended for AMDHSA OS</span><a class="headerlink" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="13%" />
<col width="6%" />
<col width="14%" />
<col width="67%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Position</th>
<th class="head">Byte
Size</th>
<th class="head">Byte
Alignment</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>1</td>
<td>8</td>
<td>8</td>
<td>OpenCL Global Offset X</td>
</tr>
<tr class="row-odd"><td>2</td>
<td>8</td>
<td>8</td>
<td>OpenCL Global Offset Y</td>
</tr>
<tr class="row-even"><td>3</td>
<td>8</td>
<td>8</td>
<td>OpenCL Global Offset Z</td>
</tr>
<tr class="row-odd"><td>4</td>
<td>8</td>
<td>8</td>
<td>OpenCL address of printf buffer</td>
</tr>
<tr class="row-even"><td>5</td>
<td>8</td>
<td>8</td>
<td>OpenCL address of virtual queue used by
enqueue_kernel.</td>
</tr>
<tr class="row-odd"><td>6</td>
<td>8</td>
<td>8</td>
<td>OpenCL address of AqlWrap struct used by
enqueue_kernel.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="hcc">
<span id="amdgpu-hcc"></span><h3><a class="toc-backref" href="#id95">HCC</a><a class="headerlink" href="#hcc" title="Permalink to this headline">¶</a></h3>
<p>When the language is HCC the following differences occur:</p>
<ol class="arabic simple">
<li>The HSA memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
</ol>
</div>
<div class="section" id="assembler">
<span id="amdgpu-assembler"></span><h3><a class="toc-backref" href="#id96">Assembler</a><a class="headerlink" href="#assembler" title="Permalink to this headline">¶</a></h3>
<p>AMDGPU backend has LLVM-MC based assembler which is currently in development.
It supports AMDGCN GFX6-GFX9.</p>
<p>This section describes general syntax for instructions and operands.</p>
<div class="section" id="instructions">
<h4><a class="toc-backref" href="#id97">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h4>
<div class="toctree-wrapper compound">
</div>
<p>An instruction has the following <a class="reference internal" href="AMDGPUInstructionSyntax.html"><span class="doc">syntax</span></a>:</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre"><</span></code><em>opcode</em><code class="docutils literal notranslate"><span class="pre">></span>    <span class="pre"><</span></code><em>operand0</em><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><em>operand1</em><code class="docutils literal notranslate"><span class="pre">>,...</span>    <span class="pre"><</span></code><em>modifier0</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>modifier1</em><code class="docutils literal notranslate"><span class="pre">>...</span></code></div></blockquote>
<p><a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">Operands</span></a> are normally comma-separated while
<a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">modifiers</span></a> are space-separated.</p>
<p>The order of <em>operands</em> and <em>modifiers</em> is fixed.
Most <em>modifiers</em> are optional and may be omitted.</p>
<p>See detailed instruction syntax description for <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a>,
<a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a> and <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a>.</p>
<p>Note that features under development are not included in this description.</p>
<p>For more information about instructions, their semantics and supported combinations of
operands, refer to one of instruction set architecture manuals
<a class="reference internal" href="#amd-gcn-gfx6" id="id39">[AMD-GCN-GFX6]</a>, <a class="reference internal" href="#amd-gcn-gfx7" id="id40">[AMD-GCN-GFX7]</a>, <a class="reference internal" href="#amd-gcn-gfx8" id="id41">[AMD-GCN-GFX8]</a> and <a class="reference internal" href="#amd-gcn-gfx9" id="id42">[AMD-GCN-GFX9]</a>.</p>
</div>
<div class="section" id="operands">
<h4><a class="toc-backref" href="#id98">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h4>
<p>Detailed description of operands may be found <a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">here</span></a>.</p>
</div>
<div class="section" id="modifiers">
<h4><a class="toc-backref" href="#id99">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h4>
<p>Detailed description of modifiers may be found <a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">here</span></a>.</p>
</div>
<div class="section" id="instruction-examples">
<h4><a class="toc-backref" href="#id100">Instruction Examples</a><a class="headerlink" href="#instruction-examples" title="Permalink to this headline">¶</a></h4>
<div class="section" id="ds">
<h5><a class="toc-backref" href="#id101">DS</a><a class="headerlink" href="#ds" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">ds_add_u32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">16</span>
<span class="nf">ds_write_src2_b64</span> <span class="nv">v2</span> <span class="nv">offset0</span><span class="p">:</span><span class="mi">4</span> <span class="nv">offset1</span><span class="p">:</span><span class="mi">8</span>
<span class="nf">ds_cmpst_f32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span><span class="p">,</span> <span class="nv">v6</span>
<span class="nf">ds_min_rtn_f64</span> <span class="nv">v</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">9</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “LDS/GDS instructions” in ISA Manual.</p>
</div>
<div class="section" id="flat">
<h5><a class="toc-backref" href="#id102">FLAT</a><a class="headerlink" href="#flat" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">flat_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">]</span>
<span class="nf">flat_store_dwordx3</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
<span class="nf">flat_atomic_swap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v5</span> <span class="nv">glc</span>
<span class="nf">flat_atomic_cmpswap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span> <span class="nv">slc</span>
<span class="nf">flat_atomic_fmax_x2</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “FLAT instructions” in ISA Manual.</p>
</div>
<div class="section" id="mubuf">
<h5><a class="toc-backref" href="#id103">MUBUF</a><a class="headerlink" href="#mubuf" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">buffer_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
<span class="nf">buffer_store_dwordx4</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">ttmp</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span> <span class="nv">offen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">glc</span> <span class="nv">tfe</span>
<span class="nf">buffer_store_format_xy</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
<span class="nf">buffer_wbinvl1</span>
<span class="nf">buffer_atomic_inc</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">11</span><span class="p">],</span> <span class="nv">s4</span> <span class="nv">idxen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">slc</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “MUBUF Instructions” in ISA Manual.</p>
</div>
<div class="section" id="smrd-smem">
<h5><a class="toc-backref" href="#id104">SMRD/SMEM</a><a class="headerlink" href="#smrd-smem" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_load_dword</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="mh">0xfc</span>
<span class="nf">s_load_dwordx8</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">15</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
<span class="nf">s_load_dwordx16</span> <span class="nv">s</span><span class="p">[</span><span class="mi">88</span><span class="p">:</span><span class="mi">103</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
<span class="nf">s_dcache_inv_vol</span>
<span class="nf">s_memtime</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “Scalar Memory Operations” in ISA Manual.</p>
</div>
<div class="section" id="sop1">
<h5><a class="toc-backref" href="#id105">SOP1</a><a class="headerlink" href="#sop1" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_mov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
<span class="nf">s_mov_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0x80000000</span>
<span class="nf">s_cmov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="mi">200</span>
<span class="nf">s_wqm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
<span class="nf">s_bcnt0_i32_b64</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
<span class="nf">s_swappc_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
<span class="nf">s_cbranch_join</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “SOP1 Instructions” in ISA Manual.</p>
</div>
<div class="section" id="sop2">
<h5><a class="toc-backref" href="#id106">SOP2</a><a class="headerlink" href="#sop2" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_add_u32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
<span class="nf">s_and_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
<span class="nf">s_cselect_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
<span class="nf">s_andn2_b32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
<span class="nf">s_lshr_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
<span class="nf">s_ashr_i32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
<span class="nf">s_bfm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
<span class="nf">s_bfe_i64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
<span class="nf">s_cbranch_g_fork</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “SOP2 Instructions” in ISA Manual.</p>
</div>
<div class="section" id="sopc">
<h5><a class="toc-backref" href="#id107">SOPC</a><a class="headerlink" href="#sopc" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_cmp_eq_i32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
<span class="nf">s_bitcmp1_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
<span class="nf">s_bitcmp0_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
<span class="nf">s_setvskip</span> <span class="nv">s3</span><span class="p">,</span> <span class="nv">s5</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “SOPC Instructions” in ISA Manual.</p>
</div>
<div class="section" id="sopp">
<h5><a class="toc-backref" href="#id108">SOPP</a><a class="headerlink" href="#sopp" title="Permalink to this headline">¶</a></h5>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_barrier</span>
<span class="nf">s_nop</span> <span class="mi">2</span>
<span class="nf">s_endpgm</span>
<span class="nf">s_waitcnt</span> <span class="mi">0</span> <span class="c1">; Wait for all counters to be 0</span>
<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">expcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">lgkmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="c1">; Equivalent to above</span>
<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="c1">; Wait for vmcnt counter to be 1.</span>
<span class="nf">s_sethalt</span> <span class="mi">9</span>
<span class="nf">s_sleep</span> <span class="mi">10</span>
<span class="nf">s_sendmsg</span> <span class="mh">0x1</span>
<span class="nf">s_sendmsg</span> <span class="nv">sendmsg</span><span class="p">(</span><span class="nv">MSG_INTERRUPT</span><span class="p">)</span>
<span class="nf">s_trap</span> <span class="mi">1</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “SOPP Instructions” in ISA Manual.</p>
<p>Unless otherwise mentioned, little verification is performed on the operands
of SOPP Instructions, so it is up to the programmer to be familiar with the
range or acceptable values.</p>
</div>
<div class="section" id="valu">
<h5><a class="toc-backref" href="#id109">VALU</a><a class="headerlink" href="#valu" title="Permalink to this headline">¶</a></h5>
<p>For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
the assembler will automatically use optimal encoding based on its operands.
To force specific encoding, one can add a suffix to the opcode of the instruction:</p>
<ul class="simple">
<li>_e32 for 32-bit VOP1/VOP2/VOPC</li>
<li>_e64 for 64-bit VOP3</li>
<li>_dpp for VOP_DPP</li>
<li>_sdwa for VOP_SDWA</li>
</ul>
<p>VOP1/VOP2/VOP3/VOPC examples:</p>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
<span class="nf">v_mov_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
<span class="nf">v_nop</span>
<span class="nf">v_cvt_f64_i32_e32</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v2</span>
<span class="nf">v_floor_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
<span class="nf">v_bfrev_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
<span class="nf">v_add_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
<span class="nf">v_mul_i32_i24_e64</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="mi">3</span>
<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">3</span><span class="p">,</span> <span class="nv">v3</span>
<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">100</span><span class="p">,</span> <span class="nv">v3</span>
<span class="nf">v_addc_u32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
<span class="nf">v_max_f16_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
</pre></div>
</div>
<p>VOP_DPP examples:</p>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">2</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">wave_shl</span><span class="p">:</span><span class="mi">1</span>
<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_mirror</span>
<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_bcast</span><span class="p">:</span><span class="mi">31</span>
<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
<span class="nf">v_add_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
<span class="nf">v_max_f16</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
</pre></div>
</div>
<p>VOP_SDWA examples:</p>
<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PRESERVE</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">DWORD</span>
<span class="nf">v_min_u32</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v1</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_1</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">DWORD</span>
<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
<span class="nf">v_fract_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">DWORD</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
<span class="nf">v_cmpx_le_u32</span> <span class="nv">vcc</span><span class="p">,</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_2</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_0</span>
</pre></div>
</div>
<p>For full list of supported instructions, refer to “Vector ALU instructions”.</p>
</div>
</div>
<div class="section" id="hsa-code-object-directives">
<h4><a class="toc-backref" href="#id110">HSA Code Object Directives</a><a class="headerlink" href="#hsa-code-object-directives" title="Permalink to this headline">¶</a></h4>
<p>AMDGPU ABI defines auxiliary data in output code object. In assembly source,
one can specify them with assembler directives.</p>
<div class="section" id="hsa-code-object-version-major-minor">
<h5><a class="toc-backref" href="#id111">.hsa_code_object_version major, minor</a><a class="headerlink" href="#hsa-code-object-version-major-minor" title="Permalink to this headline">¶</a></h5>
<p><em>major</em> and <em>minor</em> are integers that specify the version of the HSA code
object that will be generated by the assembler.</p>
</div>
<div class="section" id="hsa-code-object-isa-major-minor-stepping-vendor-arch">
<h5><a class="toc-backref" href="#id112">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a><a class="headerlink" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" title="Permalink to this headline">¶</a></h5>
<p><em>major</em>, <em>minor</em>, and <em>stepping</em> are all integers that describe the instruction
set architecture (ISA) version of the assembly program.</p>
<p><em>vendor</em> and <em>arch</em> are quoted strings. <em>vendor</em> should always be equal to
“AMD” and <em>arch</em> should always be equal to “AMDGPU”.</p>
<p>By default, the assembler will derive the ISA version, <em>vendor</em>, and <em>arch</em>
from the value of the -mcpu option that is passed to the assembler.</p>
</div>
<div class="section" id="amdgpu-hsa-kernel-name">
<h5><a class="toc-backref" href="#id113">.amdgpu_hsa_kernel (name)</a><a class="headerlink" href="#amdgpu-hsa-kernel-name" title="Permalink to this headline">¶</a></h5>
<p>This directives specifies that the symbol with given name is a kernel entry point
(label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.</p>
</div>
<div class="section" id="amd-kernel-code-t">
<h5><a class="toc-backref" href="#id114">.amd_kernel_code_t</a><a class="headerlink" href="#amd-kernel-code-t" title="Permalink to this headline">¶</a></h5>
<p>This directive marks the beginning of a list of key / value pairs that are used
to specify the amd_kernel_code_t object that will be emitted by the assembler.
The list must be terminated by the <em>.end_amd_kernel_code_t</em> directive. For
any amd_kernel_code_t values that are unspecified a default value will be
used. The default value for all keys is 0, with the following exceptions:</p>
<ul class="simple">
<li><em>kernel_code_version_major</em> defaults to 1.</li>
<li><em>machine_kind</em> defaults to 1.</li>
<li><em>machine_version_major</em>, <em>machine_version_minor</em>, and
<em>machine_version_stepping</em> are derived from the value of the -mcpu option
that is passed to the assembler.</li>
<li><em>kernel_code_entry_byte_offset</em> defaults to 256.</li>
<li><em>wavefront_size</em> defaults to 6.</li>
<li><em>kernarg_segment_alignment</em>, <em>group_segment_alignment</em>, and
<em>private_segment_alignment</em> default to 4. Note that alignments are specified
as a power of 2, so a value of <strong>n</strong> means an alignment of 2^ <strong>n</strong>.</li>
</ul>
<p>The <em>.amd_kernel_code_t</em> directive must be placed immediately after the
function label and before any instructions.</p>
<p>For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.</p>
<p>Here is an example of a minimal amd_kernel_code_t specification:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.hsa_code_object_version 1,0
.hsa_code_object_isa
.hsatext
.globl hello_world
.p2align 8
.amdgpu_hsa_kernel hello_world
hello_world:
.amd_kernel_code_t
enable_sgpr_kernarg_segment_ptr = 1
is_ptr64 = 1
compute_pgm_rsrc1_vgprs = 0
compute_pgm_rsrc1_sgprs = 0
compute_pgm_rsrc2_user_sgpr = 2
kernarg_segment_byte_size = 8
wavefront_sgpr_count = 2
workitem_vgpr_count = 3
.end_amd_kernel_code_t
s_load_dwordx2 s[0:1], s[0:1] 0x0
v_mov_b32 v0, 3.14159
s_waitcnt lgkmcnt(0)
v_mov_b32 v1, s0
v_mov_b32 v2, s1
flat_store_dword v[1:2], v0
s_endpgm
.Lfunc_end0:
.size hello_world, .Lfunc_end0-hello_world
</pre></div>
</div>
</div>
</div>
<div class="section" id="predefined-symbols-mattr-code-object-v3">
<h4><a class="toc-backref" href="#id115">Predefined Symbols (-mattr=+code-object-v3)</a><a class="headerlink" href="#predefined-symbols-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
<p>The AMDGPU assembler defines and updates some symbols automatically. These
symbols do not affect code generation.</p>
<div class="section" id="amdgcn-gfx-generation-number">
<h5><a class="toc-backref" href="#id116">.amdgcn.gfx_generation_number</a><a class="headerlink" href="#amdgcn-gfx-generation-number" title="Permalink to this headline">¶</a></h5>
<p>Set to the GFX generation number of the target being assembled for. For
example, when assembling for a “GFX9” target this will be set to the integer
value “9”. The possible GFX generation numbers are presented in
<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
</div>
<div class="section" id="amdgcn-next-free-vgpr">
<h5><a class="toc-backref" href="#id117">.amdgcn.next_free_vgpr</a><a class="headerlink" href="#amdgcn-next-free-vgpr" title="Permalink to this headline">¶</a></h5>
<p>Set to zero before assembly begins. At each instruction, if the current value
of this symbol is less than or equal to the maximum VGPR number explicitly
referenced within that instruction then the symbol value is updated to equal
that VGPR number plus one.</p>
<p>May be used to set the <cite>.amdhsa_next_free_vpgr</cite> directive in
<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>.</p>
<p>May be set at any time, e.g. manually set to zero at the start of each kernel.</p>
</div>
<div class="section" id="amdgcn-next-free-sgpr">
<h5><a class="toc-backref" href="#id118">.amdgcn.next_free_sgpr</a><a class="headerlink" href="#amdgcn-next-free-sgpr" title="Permalink to this headline">¶</a></h5>
<p>Set to zero before assembly begins. At each instruction, if the current value
of this symbol is less than or equal the maximum SGPR number explicitly
referenced within that instruction then the symbol value is updated to equal
that SGPR number plus one.</p>
<p>May be used to set the <cite>.amdhsa_next_free_spgr</cite> directive in
<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>.</p>
<p>May be set at any time, e.g. manually set to zero at the start of each kernel.</p>
</div>
</div>
<div class="section" id="code-object-directives-mattr-code-object-v3">
<h4><a class="toc-backref" href="#id119">Code Object Directives (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-directives-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
<p>Directives which begin with <code class="docutils literal notranslate"><span class="pre">.amdgcn</span></code> are valid for all <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code>
architecture processors, and are not OS-specific. Directives which begin with
<code class="docutils literal notranslate"><span class="pre">.amdhsa</span></code> are specific to <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architecture processors when the
<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS is specified. See <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a> and
<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
<div class="section" id="amdgcn-target-target">
<h5><a class="toc-backref" href="#id120">.amdgcn_target <target></a><a class="headerlink" href="#amdgcn-target-target" title="Permalink to this headline">¶</a></h5>
<p>Optional directive which declares the target supported by the containing
assembler source file. Valid values are described in
<a class="reference internal" href="#amdgpu-amdhsa-code-object-target-identification"><span class="std std-ref">Code Object Target Identification</span></a>. Used by the assembler
to validate command-line options such as <code class="docutils literal notranslate"><span class="pre">-triple</span></code>, <code class="docutils literal notranslate"><span class="pre">-mcpu</span></code>, and those
which specify target features.</p>
</div>
<div class="section" id="amdhsa-kernel-name">
<h5><a class="toc-backref" href="#id121">.amdhsa_kernel <name></a><a class="headerlink" href="#amdhsa-kernel-name" title="Permalink to this headline">¶</a></h5>
<p>Creates a correctly aligned AMDHSA kernel descriptor and a symbol,
<code class="docutils literal notranslate"><span class="pre"><name>.kd</span></code>, in the current location of the current section. Only valid when
the OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code>. <code class="docutils literal notranslate"><span class="pre"><name></span></code> must be a symbol that labels the first
instruction to execute, and does not need to be previously defined.</p>
<p>Marks the beginning of a list of directives used to generate the bytes of a
kernel descriptor, as described in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.
Directives which may appear in this list are described in
<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>. Directives may appear in any order, must
be valid for the target being assembled for, and cannot be repeated. Directives
support the range of values specified by the field they reference in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. If a directive is not specified, it is
assumed to have its default value, unless it is marked as “Required”, in which
case it is an error to omit the directive. This list of directives is
terminated by an <code class="docutils literal notranslate"><span class="pre">.end_amdhsa_kernel</span></code> directive.</p>
<blockquote>
<div><table border="1" class="docutils" id="amdhsa-kernel-directives-table">
<caption><span class="caption-text">AMDHSA Kernel Assembler Directives</span><a class="headerlink" href="#amdhsa-kernel-directives-table" title="Permalink to this table">¶</a></caption>
<colgroup>
<col width="35%" />
<col width="10%" />
<col width="8%" />
<col width="47%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Directive</th>
<th class="head">Default</th>
<th class="head">Supported On</th>
<th class="head">Description</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_group_segment_fixed_size</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls GROUP_SEGMENT_FIXED_SIZE in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_private_segment_fixed_size</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls PRIVATE_SEGMENT_FIXED_SIZE in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_private_segment_buffer</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_dispatch_ptr</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_DISPATCH_PTR in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_queue_ptr</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_QUEUE_PTR in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_kernarg_segment_ptr</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_dispatch_id</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_DISPATCH_ID in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_flat_scratch_init</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_private_segment_size</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_private_segment_wavefront_offset</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_x</span></code></td>
<td>1</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_WORKGROUP_ID_X in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_y</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_WORKGROUP_ID_Y in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_z</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_WORKGROUP_ID_Z in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_info</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_SGPR_WORKGROUP_INFO in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_vgpr_workitem_id</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_VGPR_WORKITEM_ID in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.
Possible values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_next_free_vgpr</span></code></td>
<td>Required</td>
<td>GFX6-GFX9</td>
<td>Maximum VGPR number explicitly referenced, plus one.
Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_next_free_sgpr</span></code></td>
<td>Required</td>
<td>GFX6-GFX9</td>
<td>Maximum SGPR number explicitly referenced, plus one.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_vcc</span></code></td>
<td>1</td>
<td>GFX6-GFX9</td>
<td>Whether the kernel may use the special VCC SGPR.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_flat_scratch</span></code></td>
<td>1</td>
<td>GFX7-GFX9</td>
<td>Whether the kernel may use flat instructions to access
scratch memory. Used to calculate
GRANULATED_WAVEFRONT_SGPR_COUNT in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_xnack_mask</span></code></td>
<td>Target
Feature
Specific
(+xnack)</td>
<td>GFX8-GFX9</td>
<td>Whether the kernel may trigger XNACK replay.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_round_mode_32</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls FLOAT_ROUND_MODE_32 in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
Possible values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_round_mode_16_64</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls FLOAT_ROUND_MODE_16_64 in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
Possible values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_denorm_mode_32</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls FLOAT_DENORM_MODE_32 in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
Possible values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_denorm_mode_16_64</span></code></td>
<td>3</td>
<td>GFX6-GFX9</td>
<td>Controls FLOAT_DENORM_MODE_16_64 in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.
Possible values are defined in
<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_dx10_clamp</span></code></td>
<td>1</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_DX10_CLAMP in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_ieee_mode</span></code></td>
<td>1</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_IEEE_MODE in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_fp16_overflow</span></code></td>
<td>0</td>
<td>GFX9</td>
<td>Controls FP16_OVFL in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_invalid_op</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_denorm_src</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_div_zero</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_overflow</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_underflow</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_inexact</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_int_div_zero</span></code></td>
<td>0</td>
<td>GFX6-GFX9</td>
<td>Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
</tr>
</tbody>
</table>
</div></blockquote>
</div>
<div class="section" id="amdgpu-metadata">
<h5><a class="toc-backref" href="#id122">.amdgpu_metadata</a><a class="headerlink" href="#amdgpu-metadata" title="Permalink to this headline">¶</a></h5>
<p>Optional directive which declares the contents of the <code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code>
note record (see <a class="reference internal" href="#amdgpu-elf-note-records-table-v3"><span class="std std-ref">AMDGPU Code Object V3 ELF Note Records</span></a>).</p>
<p>The contents must be in the <a class="reference internal" href="#yaml" id="id43">[YAML]</a> markup format, with the same structure and
semantics described in <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a>.</p>
<p>This directive is terminated by an <code class="docutils literal notranslate"><span class="pre">.end_amdgpu_metadata</span></code> directive.</p>
</div>
</div>
<div class="section" id="example-hsa-source-code-mattr-code-object-v3">
<h4><a class="toc-backref" href="#id123">Example HSA Source Code (-mattr=+code-object-v3)</a><a class="headerlink" href="#example-hsa-source-code-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
<p>Here is an example of a minimal assembly source file, defining one HSA kernel:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional
.text
.globl hello_world
.p2align 8
.type hello_world,@function
hello_world:
s_load_dwordx2 s[0:1], s[0:1] 0x0
v_mov_b32 v0, 3.14159
s_waitcnt lgkmcnt(0)
v_mov_b32 v1, s0
v_mov_b32 v2, s1
flat_store_dword v[1:2], v0
s_endpgm
.Lfunc_end0:
.size hello_world, .Lfunc_end0-hello_world
.rodata
.p2align 6
.amdhsa_kernel hello_world
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_next_free_vgpr .amdgcn.next_free_vgpr
.amdhsa_next_free_sgpr .amdgcn.next_free_sgpr
.end_amdhsa_kernel
.amdgpu_metadata
---
amdhsa.version:
- 1
- 0
amdhsa.kernels:
- .name: hello_world
.symbol: hello_world.kd
.kernarg_segment_size: 48
.group_segment_fixed_size: 0
.private_segment_fixed_size: 0
.kernarg_segment_align: 4
.wavefront_size: 64
.sgpr_count: 2
.vgpr_count: 3
.max_flat_workgroup_size: 256
...
.end_amdgpu_metadata
</pre></div>
</div>
</div>
</div>
</div>
<div class="section" id="additional-documentation">
<h2><a class="toc-backref" href="#id124">Additional Documentation</a><a class="headerlink" href="#additional-documentation" title="Permalink to this headline">¶</a></h2>
<table class="docutils citation" frame="void" id="amd-radeon-hd-2000-3000" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id3">[AMD-RADEON-HD-2000-3000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf">AMD R6xx shader ISA</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-radeon-hd-4000" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id4">[AMD-RADEON-HD-4000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf">AMD R7xx shader ISA</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-radeon-hd-5000" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id5">[AMD-RADEON-HD-5000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf">AMD Evergreen shader ISA</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-radeon-hd-6000" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id6">[AMD-RADEON-HD-6000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf">AMD Cayman/Trinity shader ISA</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-gcn-gfx6" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[AMD-GCN-GFX6]</td><td><em>(<a class="fn-backref" href="#id7">1</a>, <a class="fn-backref" href="#id39">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf">AMD Southern Islands Series ISA</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-gcn-gfx7" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[AMD-GCN-GFX7]</td><td><em>(<a class="fn-backref" href="#id8">1</a>, <a class="fn-backref" href="#id40">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf">AMD Sea Islands Series ISA</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-gcn-gfx8" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[AMD-GCN-GFX8]</td><td><em>(<a class="fn-backref" href="#id9">1</a>, <a class="fn-backref" href="#id41">2</a>)</em> <a class="reference external" href="http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf">AMD GCN3 Instruction Set Architecture</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-gcn-gfx9" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[AMD-GCN-GFX9]</td><td><em>(<a class="fn-backref" href="#id10">1</a>, <a class="fn-backref" href="#id42">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf">AMD “Vega” Instruction Set Architecture</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-rocm" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[AMD-ROCm]</td><td><em>(<a class="fn-backref" href="#id2">1</a>, <a class="fn-backref" href="#id21">2</a>, <a class="fn-backref" href="#id26">3</a>, <a class="fn-backref" href="#id37">4</a>)</em> <a class="reference external" href="http://gpuopen.com/compute-product/rocm/">ROCm: Open Platform for Development, Discovery and Education Around GPU Computing</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="amd-rocm-github" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[AMD-ROCm-github]</td><td><em>(<a class="fn-backref" href="#id32">1</a>, <a class="fn-backref" href="#id33">2</a>)</em> <a class="reference external" href="http://github.com/RadeonOpenCompute">ROCm github</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="hsa" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[HSA]</td><td><em>(<a class="fn-backref" href="#id1">1</a>, <a class="fn-backref" href="#id11">2</a>, <a class="fn-backref" href="#id20">3</a>, <a class="fn-backref" href="#id25">4</a>, <a class="fn-backref" href="#id29">5</a>, <a class="fn-backref" href="#id30">6</a>, <a class="fn-backref" href="#id31">7</a>, <a class="fn-backref" href="#id34">8</a>, <a class="fn-backref" href="#id36">9</a>)</em> <a class="reference external" href="http://www.hsafoundation.com/">Heterogeneous System Architecture (HSA) Foundation</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="elf" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[ELF]</td><td><em>(<a class="fn-backref" href="#id18">1</a>, <a class="fn-backref" href="#id19">2</a>)</em> <a class="reference external" href="http://www.sco.com/developers/gabi/">Executable and Linkable Format (ELF)</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="id44" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id24">[DWARF]</a></td><td><a class="reference external" href="http://dwarfstd.org/">DWARF Debugging Information Format</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="yaml" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[YAML]</td><td><em>(<a class="fn-backref" href="#id27">1</a>, <a class="fn-backref" href="#id43">2</a>)</em> <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html">YAML Ain’t Markup Language (YAML™) Version 1.2</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="msgpack" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[MsgPack]</td><td><em>(<a class="fn-backref" href="#id22">1</a>, <a class="fn-backref" href="#id23">2</a>, <a class="fn-backref" href="#id28">3</a>)</em> <a class="reference external" href="http://www.msgpack.org/">Message Pack</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="id45" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[OpenCL]</td><td><em>(<a class="fn-backref" href="#id13">1</a>, <a class="fn-backref" href="#id35">2</a>)</em> <a class="reference external" href="http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf">The OpenCL Specification Version 2.0</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="hrf" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label"><a class="fn-backref" href="#id12">[HRF]</a></td><td><a class="reference external" href="http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf">Heterogeneous-race-free Memory Models</a></td></tr>
</tbody>
</table>
<table class="docutils citation" frame="void" id="clang-attr" rules="none">
<colgroup><col class="label" /><col /></colgroup>
<tbody valign="top">
<tr><td class="label">[CLANG-ATTR]</td><td><em>(<a class="fn-backref" href="#id14">1</a>, <a class="fn-backref" href="#id15">2</a>, <a class="fn-backref" href="#id16">3</a>, <a class="fn-backref" href="#id17">4</a>)</em> <a class="reference external" href="http://clang.llvm.org/docs/AttributeReference.html">Attributes in Clang</a></td></tr>
</tbody>
</table>
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