diff -Naur linux-2.6.18/drivers/net/bnx2.c linux-2.6.18.bnx2/drivers/net/bnx2.c --- linux-2.6.18/drivers/net/bnx2.c 2006-09-20 05:42:06.000000000 +0200 +++ linux-2.6.18.bnx2/drivers/net/bnx2.c 2007-07-19 00:03:15.000000000 +0200 @@ -9,9 +9,23 @@ * Written by: Michael Chan (mchan@broadcom.com) */ +#include <linux/version.h> + +#if (LINUX_VERSION_CODE < 0x020613) +#include <linux/config.h> +#endif + +#if (LINUX_VERSION_CODE < 0x020500) +#if defined(CONFIG_MODVERSIONS) && defined(MODULE) && ! defined(MODVERSIONS) +#define MODVERSIONS +#include <linux/modversions.h> +#endif +#endif #include <linux/module.h> +#if (LINUX_VERSION_CODE >= 0x020600) #include <linux/moduleparam.h> +#endif #include <linux/kernel.h> #include <linux/timer.h> @@ -25,7 +39,9 @@ #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/skbuff.h> +#if (LINUX_VERSION_CODE >= 0x020600) #include <linux/dma-mapping.h> +#endif #include <asm/bitops.h> #include <asm/io.h> #include <asm/irq.h> @@ -45,8 +61,12 @@ #include <net/checksum.h> #define BCM_TSO 1 #endif +#if (LINUX_VERSION_CODE >= 0x020600) #include <linux/workqueue.h> +#endif +#ifndef BNX2_BOOT_DISK #include <linux/crc32.h> +#endif #include <linux/prefetch.h> #include <linux/cache.h> #include <linux/zlib.h> @@ -56,8 +76,8 @@ #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.4.44" -#define DRV_MODULE_RELDATE "August 10, 2006" +#define DRV_MODULE_VERSION "1.4.51b" +#define DRV_MODULE_RELDATE "December 15, 2006" #define RUN_AT(x) (jiffies + (x)) @@ -72,10 +92,12 @@ MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); +#if (LINUX_VERSION_CODE >= 0x20600) static int disable_msi = 0; module_param(disable_msi, int, 0); MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); +#endif typedef enum { BCM5706 = 0, @@ -148,7 +170,7 @@ SAIFUN_FLASH_BYTE_ADDR_MASK, 0, "Entry 0100"}, /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ - {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, @@ -207,14 +229,33 @@ MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); +#ifdef BNX2_BOOT_DISK +u32 ether_crc_le(size_t len, unsigned char const *p) +{ + u32 crc = ~0; + int i; +#define CRCPOLY_LE 0xedb88320 + + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + return crc; +} +#endif + static inline u32 bnx2_tx_avail(struct bnx2 *bp) { u32 diff; smp_mb(); - diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons); - if (diff > MAX_TX_DESC_CNT) - diff = (diff & MAX_TX_DESC_CNT) - 1; + diff = bp->tx_prod - bp->tx_cons; + if (unlikely(diff >= TX_DESC_CNT)) { + diff &= 0xffff; + if (diff == TX_DESC_CNT) + diff = MAX_TX_DESC_CNT; + } return (bp->tx_ring_size - diff); } @@ -317,7 +358,7 @@ BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); - + for (i = 0; i < 50; i++) { udelay(10); @@ -372,7 +413,11 @@ { atomic_inc(&bp->intr_sem); bnx2_disable_int(bp); +#if (LINUX_VERSION_CODE >= 0x2051c) synchronize_irq(bp->pdev->irq); +#else + synchronize_irq(); +#endif } static void @@ -434,11 +479,12 @@ { int i, status_blk_size; - bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT, + bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT, GFP_KERNEL); if (bp->tx_buf_ring == NULL) return -ENOMEM; + memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT); bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, sizeof(struct tx_bd) * TX_DESC_CNT, @@ -585,7 +631,7 @@ u32 local_adv, remote_adv; bp->flow_ctrl = 0; - if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != + if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { if (bp->duplex == DUPLEX_FULL) { @@ -860,7 +906,7 @@ u32 bmsr; u8 link_up; - if (bp->loopback == MAC_LOOPBACK) { + if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) { bp->link_up = 1; return 0; } @@ -902,6 +948,7 @@ u32 bmcr; bnx2_read_phy(bp, MII_BMCR, &bmcr); + bmcr &= ~BCM5708S_BMCR_FORCE_2500; if (!(bmcr & BMCR_ANENABLE)) { bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANENABLE); @@ -988,7 +1035,21 @@ u32 new_bmcr; int force_link_down = 0; - if (CHIP_NUM(bp) == CHIP_NUM_5708) { + bnx2_read_phy(bp, MII_ADVERTISE, &adv); + adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500); + new_bmcr |= BMCR_SPEED1000; + if (bp->req_line_speed == SPEED_2500) { + new_bmcr |= BCM5708S_BMCR_FORCE_2500; + bnx2_read_phy(bp, BCM5708S_UP1, &up1); + if (!(up1 & BCM5708S_UP1_2G5)) { + up1 |= BCM5708S_UP1_2G5; + bnx2_write_phy(bp, BCM5708S_UP1, up1); + force_link_down = 1; + } + } else if (CHIP_NUM(bp) == CHIP_NUM_5708) { bnx2_read_phy(bp, BCM5708S_UP1, &up1); if (up1 & BCM5708S_UP1_2G5) { up1 &= ~BCM5708S_UP1_2G5; @@ -997,12 +1058,6 @@ } } - bnx2_read_phy(bp, MII_ADVERTISE, &adv); - adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF); - - bnx2_read_phy(bp, MII_BMCR, &bmcr); - new_bmcr = bmcr & ~BMCR_ANENABLE; - new_bmcr |= BMCR_SPEED1000; if (bp->req_duplex == DUPLEX_FULL) { adv |= ADVERTISE_1000XFULL; new_bmcr |= BMCR_FULLDPLX; @@ -1023,9 +1078,13 @@ bp->link_up = 0; netif_carrier_off(bp->dev); bnx2_write_phy(bp, MII_BMCR, new_bmcr); + bnx2_report_link(bp); } bnx2_write_phy(bp, MII_ADVERTISE, adv); bnx2_write_phy(bp, MII_BMCR, new_bmcr); + } else { + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); } return 0; } @@ -1048,30 +1107,30 @@ if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { /* Force a link down visible on the other side */ if (bp->link_up) { - int i; - bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); - for (i = 0; i < 110; i++) { - udelay(100); - } + spin_unlock_bh(&bp->phy_lock); + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 50); + spin_lock_bh(&bp->phy_lock); } bnx2_write_phy(bp, MII_ADVERTISE, new_adv); bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); - if (CHIP_NUM(bp) == CHIP_NUM_5706) { - /* Speed up link-up time when the link partner - * does not autonegotiate which is very common - * in blade servers. Some blade servers use - * IPMI for kerboard input and it's important - * to minimize link disruptions. Autoneg. involves - * exchanging base pages plus 3 next pages and - * normally completes in about 120 msec. - */ - bp->current_interval = SERDES_AN_TIMEOUT; - bp->serdes_an_pending = 1; - mod_timer(&bp->timer, jiffies + bp->current_interval); - } + /* Speed up link-up time when the link partner + * does not autonegotiate which is very common + * in blade servers. Some blade servers use + * IPMI for kerboard input and it's important + * to minimize link disruptions. Autoneg. involves + * exchanging base pages plus 3 next pages and + * normally completes in about 120 msec. + */ + bp->current_interval = SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); + } else { + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); } return 0; @@ -1087,7 +1146,7 @@ #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) - + #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) static int @@ -1120,7 +1179,7 @@ new_adv_reg |= ADVERTISE_100FULL; if (bp->advertising & ADVERTISED_1000baseT_Full) new_adv1000_reg |= ADVERTISE_1000FULL; - + new_adv_reg |= ADVERTISE_CSMA; new_adv_reg |= bnx2_phy_get_pause_adv(bp); @@ -1153,20 +1212,20 @@ } if (new_bmcr != bmcr) { u32 bmsr; - int i = 0; bnx2_read_phy(bp, MII_BMSR, &bmsr); bnx2_read_phy(bp, MII_BMSR, &bmsr); - + if (bmsr & BMSR_LSTATUS) { /* Force link down */ bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); - do { - udelay(100); - bnx2_read_phy(bp, MII_BMSR, &bmsr); - bnx2_read_phy(bp, MII_BMSR, &bmsr); - i++; - } while ((bmsr & BMSR_LSTATUS) && (i < 620)); + spin_unlock_bh(&bp->phy_lock); + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 20); + spin_lock_bh(&bp->phy_lock); + + bnx2_read_phy(bp, MII_BMSR, &bmsr); + bnx2_read_phy(bp, MII_BMSR, &bmsr); } bnx2_write_phy(bp, MII_BMCR, new_bmcr); @@ -1181,6 +1240,9 @@ bnx2_resolve_flow_ctrl(bp); bnx2_set_mac_link(bp); } + } else { + bnx2_resolve_flow_ctrl(bp); + bnx2_set_mac_link(bp); } return 0; } @@ -1397,7 +1459,8 @@ for (i = 0; i < 10; i++) { if (bnx2_test_link(bp) == 0) break; - udelay(10); + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 10); } mac_mode = REG_RD(bp, BNX2_EMAC_MODE); @@ -1424,7 +1487,8 @@ /* wait for an acknowledgement. */ for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) { - msleep(10); + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 100); val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB); @@ -1547,7 +1611,7 @@ } static void -bnx2_set_mac_addr(struct bnx2 *bp) +bnx2_set_mac_addr(struct bnx2 *bp) { u32 val; u8 *mac_addr = bp->dev->dev_addr; @@ -1556,7 +1620,7 @@ REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); - val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | (mac_addr[4] << 8) | mac_addr[5]; REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); @@ -1884,11 +1948,16 @@ } +#ifdef CONFIG_PCI_MSI /* MSI ISR - The only difference between this and the INTx ISR * is that the MSI interrupt is always serviced. */ static irqreturn_t +#if (LINUX_VERSION_CODE >= 0x20613) +bnx2_msi(int irq, void *dev_instance) +#else bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) +#endif { struct net_device *dev = dev_instance; struct bnx2 *bp = netdev_priv(dev); @@ -1906,9 +1975,14 @@ return IRQ_HANDLED; } +#endif static irqreturn_t +#if (LINUX_VERSION_CODE >= 0x20613) +bnx2_interrupt(int irq, void *dev_instance) +#else bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs) +#endif { struct net_device *dev = dev_instance; struct bnx2 *bp = netdev_priv(dev); @@ -1984,12 +2058,12 @@ if (orig_budget > dev->quota) orig_budget = dev->quota; - + work_done = bnx2_rx_int(bp, orig_budget); *budget -= work_done; dev->quota -= work_done; } - + bp->last_status_idx = bp->status_blk->status_idx; rmb(); @@ -2040,7 +2114,8 @@ if (dev->flags & IFF_PROMISC) { /* Promiscuous mode. */ rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; - sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN; + sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN | + BNX2_RPM_SORT_USER0_PROM_VLAN; } else if (dev->flags & IFF_ALLMULTI) { for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { @@ -2322,7 +2397,7 @@ cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_RXP_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - + fw.ver_major = bnx2_RXP_b06FwReleaseMajor; fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; fw.ver_fix = bnx2_RXP_b06FwReleaseFix; @@ -2374,7 +2449,7 @@ cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_TXP_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - + fw.ver_major = bnx2_TXP_b06FwReleaseMajor; fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; fw.ver_fix = bnx2_TXP_b06FwReleaseFix; @@ -2426,7 +2501,7 @@ cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_TPAT_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - + fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; @@ -2478,7 +2553,7 @@ cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; cpu_reg.spad_base = BNX2_COM_SCRATCH; cpu_reg.mips_view_base = 0x8000000; - + fw.ver_major = bnx2_COM_b06FwReleaseMajor; fw.ver_minor = bnx2_COM_b06FwReleaseMinor; fw.ver_fix = bnx2_COM_b06FwReleaseFix; @@ -2537,9 +2612,11 @@ (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | PCI_PM_CTRL_PME_STATUS); - if (pmcsr & PCI_PM_CTRL_STATE_MASK) + if (pmcsr & PCI_PM_CTRL_STATE_MASK) { /* delay required during transition out of D3hot */ - msleep(20); + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 50); + } val = REG_RD(bp, BNX2_EMAC_MODE); val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; @@ -2741,7 +2818,7 @@ val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); /* Enable both bits, even on read. */ - REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); } @@ -2752,7 +2829,7 @@ val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); /* Disable both bits, even after read. */ - REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, + REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, val & ~(BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN)); } @@ -3081,7 +3158,7 @@ int buf_size) { u32 written, offset32, len32; - u8 *buf, start[4], end[4], *flash_buffer = NULL; + u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL; int rc = 0; int align_start, align_end; @@ -3092,7 +3169,7 @@ if ((align_start = (offset32 & 3))) { offset32 &= ~3; - len32 += align_start; + len32 += (4 - align_start); if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) return rc; } @@ -3109,16 +3186,17 @@ } if (align_start || align_end) { - buf = kmalloc(len32, GFP_KERNEL); - if (buf == 0) + align_buf = kmalloc(len32, GFP_KERNEL); + if (align_buf == NULL) return -ENOMEM; if (align_start) { - memcpy(buf, start, 4); + memcpy(align_buf, start, 4); } if (align_end) { - memcpy(buf + len32 - 4, end, 4); + memcpy(align_buf + len32 - 4, end, 4); } - memcpy(buf + align_start, data_buf, buf_size); + memcpy(align_buf + align_start, data_buf, buf_size); + buf = align_buf; } if (bp->flash_info->buffered == 0) { @@ -3143,7 +3221,7 @@ /* Find the data_start addr */ data_start = (written == 0) ? offset32 : page_start; /* Find the data_end addr */ - data_end = (page_end > offset32 + len32) ? + data_end = (page_end > offset32 + len32) ? (offset32 + len32) : page_end; /* Request access to the flash interface. */ @@ -3164,8 +3242,8 @@ cmd_flags |= BNX2_NVM_COMMAND_LAST; } rc = bnx2_nvram_read_dword(bp, - page_start + j, - &flash_buffer[j], + page_start + j, + &flash_buffer[j], cmd_flags); if (rc) @@ -3192,7 +3270,7 @@ if (bp->flash_info->buffered == 0) { for (addr = page_start; addr < data_start; addr += 4, i += 4) { - + rc = bnx2_nvram_write_dword(bp, addr, &flash_buffer[i], cmd_flags); @@ -3226,7 +3304,7 @@ if (bp->flash_info->buffered == 0) { for (addr = data_end; addr < page_end; addr += 4, i += 4) { - + if (addr == page_end-4) { cmd_flags = BNX2_NVM_COMMAND_LAST; } @@ -3252,11 +3330,8 @@ } nvram_write_end: - if (bp->flash_info->buffered == 0) - kfree(flash_buffer); - - if (align_start || align_end) - kfree(buf); + kfree(flash_buffer); + kfree(align_buf); return rc; } @@ -3296,8 +3371,10 @@ REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || - (CHIP_ID(bp) == CHIP_ID_5706_A1)) - msleep(15); + (CHIP_ID(bp) == CHIP_ID_5706_A1)) { + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 50); + } /* Reset takes approximate 30 usec */ for (i = 0; i < 10; i++) { @@ -3351,9 +3428,9 @@ val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | BNX2_DMA_CONFIG_DATA_WORD_SWAP | #ifdef __BIG_ENDIAN - BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | + BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | #endif - BNX2_DMA_CONFIG_CNTL_WORD_SWAP | + BNX2_DMA_CONFIG_CNTL_WORD_SWAP | DMA_READ_CHANS << 12 | DMA_WRITE_CHANS << 16; @@ -3446,7 +3523,7 @@ REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, (u64) bp->stats_blk_mapping >> 32); - REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, + REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, @@ -3511,7 +3588,7 @@ bp->tx_wake_thresh = bp->tx_ring_size / 2; txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; - + txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; @@ -3519,7 +3596,7 @@ bp->tx_cons = 0; bp->hw_tx_cons = 0; bp->tx_prod_bseq = 0; - + val = BNX2_L2CTX_TYPE_TYPE_L2; val |= BNX2_L2CTX_TYPE_SIZE_L2; CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val); @@ -3540,7 +3617,7 @@ { struct rx_bd *rxbd; int i; - u16 prod, ring_prod; + u16 prod, ring_prod; u32 val; /* 8 for CRC and VLAN */ @@ -3552,7 +3629,7 @@ bp->rx_cons = 0; bp->hw_rx_cons = 0; bp->rx_prod_bseq = 0; - + for (i = 0; i < bp->rx_max_ring; i++) { int j; @@ -3712,7 +3789,9 @@ if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) return rc; + spin_lock_bh(&bp->phy_lock); bnx2_init_phy(bp); + spin_unlock_bh(&bp->phy_lock); bnx2_set_link(bp); return 0; } @@ -3927,7 +4006,7 @@ return ret; } } - + return ret; } @@ -3952,7 +4031,7 @@ bnx2_set_mac_loopback(bp); } else if (loopback_mode == BNX2_PHY_LOOPBACK) { - bp->loopback = 0; + bp->loopback = PHY_LOOPBACK; bnx2_set_phy_loopback(bp); } else @@ -3963,7 +4042,7 @@ if (!skb) return -ENOMEM; packet = skb_put(skb, pkt_size); - memcpy(packet, bp->mac_addr, 6); + memcpy(packet, bp->dev->dev_addr, 6); memset(packet + 6, 0x0, 8); for (i = 14; i < pkt_size; i++) packet[i] = (unsigned char) (i & 0xff); @@ -4124,7 +4203,7 @@ bnx2_read_phy(bp, MII_BMSR, &bmsr); bnx2_read_phy(bp, MII_BMSR, &bmsr); spin_unlock_bh(&bp->phy_lock); - + if (bmsr & BMSR_LSTATUS) { return 0; } @@ -4153,7 +4232,8 @@ break; } - msleep_interruptible(10); + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(HZ / 100); } if (i < 10) return 0; @@ -4162,81 +4242,118 @@ } static void -bnx2_timer(unsigned long data) +bnx2_5706_serdes_timer(struct bnx2 *bp) { - struct bnx2 *bp = (struct bnx2 *) data; - u32 msg; + spin_lock(&bp->phy_lock); + if (bp->serdes_an_pending) + bp->serdes_an_pending--; + else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { + u32 bmcr; - if (!netif_running(bp->dev)) - return; + bp->current_interval = bp->timer_interval; - if (atomic_read(&bp->intr_sem) != 0) - goto bnx2_restart_timer; + bnx2_read_phy(bp, MII_BMCR, &bmcr); - msg = (u32) ++bp->fw_drv_pulse_wr_seq; - REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg); + if (bmcr & BMCR_ANENABLE) { + u32 phy1, phy2; - bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); + bnx2_write_phy(bp, 0x1c, 0x7c00); + bnx2_read_phy(bp, 0x1c, &phy1); - if ((bp->phy_flags & PHY_SERDES_FLAG) && - (CHIP_NUM(bp) == CHIP_NUM_5706)) { + bnx2_write_phy(bp, 0x17, 0x0f01); + bnx2_read_phy(bp, 0x15, &phy2); + bnx2_write_phy(bp, 0x17, 0x0f01); + bnx2_read_phy(bp, 0x15, &phy2); - spin_lock(&bp->phy_lock); - if (bp->serdes_an_pending) { - bp->serdes_an_pending--; + if ((phy1 & 0x10) && /* SIGNAL DETECT */ + !(phy2 & 0x20)) { /* no CONFIG */ + + bmcr &= ~BMCR_ANENABLE; + bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; + bnx2_write_phy(bp, MII_BMCR, bmcr); + bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG; + } } - else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { + } + else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && + (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { + u32 phy2; + + bnx2_write_phy(bp, 0x17, 0x0f01); + bnx2_read_phy(bp, 0x15, &phy2); + if (phy2 & 0x20) { u32 bmcr; - bp->current_interval = bp->timer_interval; - bnx2_read_phy(bp, MII_BMCR, &bmcr); + bmcr |= BMCR_ANENABLE; + bnx2_write_phy(bp, MII_BMCR, bmcr); - if (bmcr & BMCR_ANENABLE) { - u32 phy1, phy2; + bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; + } + } else + bp->current_interval = bp->timer_interval; - bnx2_write_phy(bp, 0x1c, 0x7c00); - bnx2_read_phy(bp, 0x1c, &phy1); + spin_unlock(&bp->phy_lock); +} - bnx2_write_phy(bp, 0x17, 0x0f01); - bnx2_read_phy(bp, 0x15, &phy2); - bnx2_write_phy(bp, 0x17, 0x0f01); - bnx2_read_phy(bp, 0x15, &phy2); - - if ((phy1 & 0x10) && /* SIGNAL DETECT */ - !(phy2 & 0x20)) { /* no CONFIG */ - - bmcr &= ~BMCR_ANENABLE; - bmcr |= BMCR_SPEED1000 | - BMCR_FULLDPLX; - bnx2_write_phy(bp, MII_BMCR, bmcr); - bp->phy_flags |= - PHY_PARALLEL_DETECT_FLAG; - } - } +static void +bnx2_5708_serdes_timer(struct bnx2 *bp) +{ + if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) { + bp->serdes_an_pending = 0; + return; + } + + spin_lock(&bp->phy_lock); + if (bp->serdes_an_pending) + bp->serdes_an_pending--; + else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { + u32 bmcr; + + bnx2_read_phy(bp, MII_BMCR, &bmcr); + + if (bmcr & BMCR_ANENABLE) { + bmcr &= ~BMCR_ANENABLE; + bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500; + bnx2_write_phy(bp, MII_BMCR, bmcr); + bp->current_interval = SERDES_FORCED_TIMEOUT; + } else { + bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500); + bmcr |= BMCR_ANENABLE; + bnx2_write_phy(bp, MII_BMCR, bmcr); + bp->serdes_an_pending = 2; + bp->current_interval = bp->timer_interval; } - else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && - (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { - u32 phy2; - bnx2_write_phy(bp, 0x17, 0x0f01); - bnx2_read_phy(bp, 0x15, &phy2); - if (phy2 & 0x20) { - u32 bmcr; + } else + bp->current_interval = bp->timer_interval; - bnx2_read_phy(bp, MII_BMCR, &bmcr); - bmcr |= BMCR_ANENABLE; - bnx2_write_phy(bp, MII_BMCR, bmcr); + spin_unlock(&bp->phy_lock); +} - bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; +static void +bnx2_timer(unsigned long data) +{ + struct bnx2 *bp = (struct bnx2 *) data; + u32 msg; - } - } - else - bp->current_interval = bp->timer_interval; + if (!netif_running(bp->dev)) + return; - spin_unlock(&bp->phy_lock); - } + if (atomic_read(&bp->intr_sem) != 0) + goto bnx2_restart_timer; + + msg = (u32) ++bp->fw_drv_pulse_wr_seq; + REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg); + + bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT); + + if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5706)) + bnx2_5706_serdes_timer(bp); + else if ((bp->phy_flags & PHY_SERDES_FLAG) && + (CHIP_NUM(bp) == CHIP_NUM_5708)) + bnx2_5708_serdes_timer(bp); bnx2_restart_timer: mod_timer(&bp->timer, jiffies + bp->current_interval); @@ -4249,6 +4366,8 @@ struct bnx2 *bp = netdev_priv(dev); int rc; + netif_carrier_off(dev); + bnx2_set_power_state(bp, PCI_D0); bnx2_disable_int(bp); @@ -4256,6 +4375,7 @@ if (rc) return rc; +#ifdef CONFIG_PCI_MSI if ((CHIP_ID(bp) != CHIP_ID_5706_A0) && (CHIP_ID(bp) != CHIP_ID_5706_A1) && !disable_msi) { @@ -4270,7 +4390,9 @@ IRQF_SHARED, dev->name, dev); } } - else { + else +#endif + { rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED, dev->name, dev); } @@ -4283,21 +4405,24 @@ if (rc) { free_irq(bp->pdev->irq, dev); +#ifdef CONFIG_PCI_MSI if (bp->flags & USING_MSI_FLAG) { pci_disable_msi(bp->pdev); bp->flags &= ~USING_MSI_FLAG; } +#endif bnx2_free_skbs(bp); bnx2_free_mem(bp); return rc; } - + mod_timer(&bp->timer, jiffies + bp->current_interval); atomic_set(&bp->intr_sem, 0); bnx2_enable_int(bp); +#ifdef CONFIG_PCI_MSI if (bp->flags & USING_MSI_FLAG) { /* Test MSI to make sure it is working * If MSI test fails, go back to INTx mode @@ -4332,6 +4457,7 @@ if (bp->flags & USING_MSI_FLAG) { printk(KERN_INFO PFX "%s: using MSI\n", dev->name); } +#endif netif_start_queue(dev); @@ -4362,7 +4488,11 @@ struct bnx2 *bp = netdev_priv(dev); /* This allows the netif to be shutdown gracefully before resetting */ +#if (LINUX_VERSION_CODE >= 0x20600) schedule_work(&bp->reset_task); +#else + schedule_task(&bp->reset_task); +#endif } #ifdef BCM_VLAN @@ -4396,6 +4526,93 @@ } #endif +/* Test for DMA addresses > 40-bit. + * Only 64-bit systems without IOMMU requires DMA address checking. + */ +static inline int bnx2_40bit_overflow_test(struct bnx2 *bp, dma_addr_t mapping, + int len) +{ +#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) + if (CHIP_NUM(bp) == CHIP_NUM_5708) + return (((u64) mapping + len) > DMA_40BIT_MASK); + return 0; +#else + return 0; +#endif +} + +#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) +/* Workaround 40-bit hardware DMA bugs. */ +static int bnx2_dma_hwbug_workaround(struct bnx2 *bp, struct sk_buff **skb, + u16 *last_plus_one, u32 base_flags, + u32 mss) +{ + struct sk_buff *new_skb = skb_copy(*skb, GFP_ATOMIC); + dma_addr_t new_addr = 0; + int i, ret = 0; + u16 hw_prod = *last_plus_one; + u16 start, hw_start, prod; + + prod = TX_RING_IDX(hw_prod); + start = prod - 1 - skb_shinfo(*skb)->nr_frags; + hw_start = hw_prod - 1 - skb_shinfo(*skb)->nr_frags; + start &= MAX_TX_DESC_CNT; + if (start > prod) { + start--; + hw_start--; + } + + if (!new_skb) { + ret = -1; + } else { + struct tx_bd *txbd; + + /* New SKB is guaranteed to be linear. */ + new_addr = pci_map_single(bp->pdev, new_skb->data, new_skb->len, + PCI_DMA_TODEVICE); + txbd = &bp->tx_desc_ring[start]; + + txbd->tx_bd_haddr_hi = (u64) new_addr >> 32; + txbd->tx_bd_haddr_lo = (u64) new_addr & 0xffffffff; + txbd->tx_bd_mss_nbytes = new_skb->len | (mss << 16); + txbd->tx_bd_vlan_tag_flags = base_flags | TX_BD_FLAGS_START | + TX_BD_FLAGS_END; + + *last_plus_one = NEXT_TX_BD(hw_start); + } + + /* Now clean up the sw ring entries. */ + i = 0; + while (start != prod) { + int len; + + if (i == 0) + len = skb_headlen(*skb); + else + len = skb_shinfo(*skb)->frags[i-1].size; + + pci_unmap_single(bp->pdev, + pci_unmap_addr(&tp->tx_buf_ring[start], + mapping), + len, PCI_DMA_TODEVICE); + if (i == 0) { + bp->tx_buf_ring[start].skb = new_skb; + pci_unmap_addr_set(&bp->tx_buf_ring[start], mapping, + new_addr); + } + hw_start = NEXT_TX_BD(hw_start); + start = TX_RING_IDX(hw_start); + i++; + } + + dev_kfree_skb(*skb); + + *skb = new_skb; + + return ret; +} +#endif + /* Called with netif_tx_lock. * bnx2_tx_int() runs without netif_tx_lock unless it needs to call * netif_wake_queue(). @@ -4409,7 +4626,7 @@ struct sw_bd *tx_buf; u32 len, vlan_tag_flags, last_frag, mss; u16 prod, ring_prod; - int i; + int i, would_hit_hwbug = 0; if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) { netif_stop_queue(dev); @@ -4423,24 +4640,28 @@ ring_prod = TX_RING_IDX(prod); vlan_tag_flags = 0; - if (skb->ip_summed == CHECKSUM_HW) { + if (skb->ip_summed == CHECKSUM_PARTIAL) { vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; } +#ifdef BCM_VLAN if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) { vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); } +#endif #ifdef BCM_TSO if ((mss = skb_shinfo(skb)->gso_size) && (skb->len > (bp->dev->mtu + ETH_HLEN))) { u32 tcp_opt_len, ip_tcp_len; +#if (LINUX_VERSION_CODE > 0x2060b) if (skb_header_cloned(skb) && pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { dev_kfree_skb(skb); return NETDEV_TX_OK; } +#endif tcp_opt_len = ((skb->h.th->doff - 5) * 4); vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; @@ -4470,7 +4691,7 @@ } mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); - + tx_buf = &bp->tx_buf_ring[ring_prod]; tx_buf->skb = skb; pci_unmap_addr_set(tx_buf, mapping, mapping); @@ -4502,10 +4723,25 @@ txbd->tx_bd_mss_nbytes = len | (mss << 16); txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; + if (bnx2_40bit_overflow_test(bp, mapping, len)) + would_hit_hwbug = 1; } txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; prod = NEXT_TX_BD(prod); + +#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) + if (unlikely(would_hit_hwbug)) { + /* If the workaround fails due to memory/mapping + * failure, silently drop this packet. + */ + if (bnx2_dma_hwbug_workaround(bp, &skb, &prod, + vlan_tag_flags, mss)) + return NETDEV_TX_OK; + + } +#endif + bp->tx_prod_bseq += skb->len; REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); @@ -4536,8 +4772,10 @@ * linkwatch_event() may be on the workqueue and it will try to get * the rtnl_lock which we are holding. */ - while (bp->in_reset_task) - msleep(1); + while (bp->in_reset_task) { + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(1); + } bnx2_netif_stop(bp); del_timer_sync(&bp->timer); @@ -4549,10 +4787,12 @@ reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; bnx2_reset_chip(bp, reset_code); free_irq(bp->pdev->irq, dev); +#ifdef CONFIG_PCI_MSI if (bp->flags & USING_MSI_FLAG) { pci_disable_msi(bp->pdev); bp->flags &= ~USING_MSI_FLAG; } +#endif bnx2_free_skbs(bp); bnx2_free_mem(bp); bp->link_up = 0; @@ -4600,23 +4840,23 @@ net_stats->tx_bytes = GET_NET_STATS(stats_blk->stat_IfHCOutOctets); - net_stats->multicast = + net_stats->multicast = GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts); - net_stats->collisions = + net_stats->collisions = (unsigned long) stats_blk->stat_EtherStatsCollisions; - net_stats->rx_length_errors = + net_stats->rx_length_errors = (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts + stats_blk->stat_EtherStatsOverrsizePkts); - net_stats->rx_over_errors = + net_stats->rx_over_errors = (unsigned long) stats_blk->stat_IfInMBUFDiscards; - net_stats->rx_frame_errors = + net_stats->rx_frame_errors = (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors; - net_stats->rx_crc_errors = + net_stats->rx_crc_errors = (unsigned long) stats_blk->stat_Dot3StatsFCSErrors; net_stats->rx_errors = net_stats->rx_length_errors + @@ -4637,7 +4877,7 @@ } net_stats->tx_errors = - (unsigned long) + (unsigned long) stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + net_stats->tx_aborted_errors + @@ -4698,7 +4938,7 @@ return 0; } - + static int bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) { @@ -4711,7 +4951,7 @@ if (cmd->autoneg == AUTONEG_ENABLE) { autoneg |= AUTONEG_SPEED; - cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; + cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; /* allow advertising 1 speed */ if ((cmd->advertising == ADVERTISED_10baseT_Half) || @@ -4743,10 +4983,14 @@ } else { if (bp->phy_flags & PHY_SERDES_FLAG) { - if ((cmd->speed != SPEED_1000) || - (cmd->duplex != DUPLEX_FULL)) { + if ((cmd->speed != SPEED_1000 && + cmd->speed != SPEED_2500) || + (cmd->duplex != DUPLEX_FULL)) + return -EINVAL; + + if (cmd->speed == SPEED_2500 && + !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) return -EINVAL; - } } else if (cmd->speed == SPEED_1000) { return -EINVAL; @@ -4900,14 +5144,13 @@ bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); spin_unlock_bh(&bp->phy_lock); - msleep(20); + current->state = TASK_UNINTERRUPTIBLE; + schedule_timeout(HZ / 50); spin_lock_bh(&bp->phy_lock); - if (CHIP_NUM(bp) == CHIP_NUM_5706) { - bp->current_interval = SERDES_AN_TIMEOUT; - bp->serdes_an_pending = 1; - mod_timer(&bp->timer, jiffies + bp->current_interval); - } + bp->current_interval = SERDES_AN_TIMEOUT; + bp->serdes_an_pending = 1; + mod_timer(&bp->timer, jiffies + bp->current_interval); } bnx2_read_phy(bp, MII_BMCR, &bmcr); @@ -4919,6 +5162,7 @@ return 0; } +#if (LINUX_VERSION_CODE >= 0x20418) static int bnx2_get_eeprom_len(struct net_device *dev) { @@ -4929,7 +5173,9 @@ return (int) bp->flash_size; } +#endif +#ifdef ETHTOOL_GEEPROM static int bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *eebuf) @@ -4943,7 +5189,9 @@ return rc; } +#endif +#ifdef ETHTOOL_SEEPROM static int bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *eebuf) @@ -4957,6 +5205,7 @@ return rc; } +#endif static int bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) @@ -4988,7 +5237,7 @@ bp->rx_ticks = (u16) coal->rx_coalesce_usecs; if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; - bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; + bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; @@ -5129,6 +5378,7 @@ return 0; } +#ifdef BCM_TSO static int bnx2_set_tso(struct net_device *dev, u32 data) { @@ -5138,6 +5388,7 @@ dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN); return 0; } +#endif #define BNX2_NUM_STATS 46 @@ -5206,46 +5457,46 @@ STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), - STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), - STATS_OFFSET32(stat_Dot3StatsFCSErrors), - STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), - STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), - STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), - STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), - STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), - STATS_OFFSET32(stat_Dot3StatsLateCollisions), - STATS_OFFSET32(stat_EtherStatsCollisions), - STATS_OFFSET32(stat_EtherStatsFragments), - STATS_OFFSET32(stat_EtherStatsJabbers), - STATS_OFFSET32(stat_EtherStatsUndersizePkts), - STATS_OFFSET32(stat_EtherStatsOverrsizePkts), - STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), - STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), - STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), - STATS_OFFSET32(stat_XonPauseFramesReceived), - STATS_OFFSET32(stat_XoffPauseFramesReceived), - STATS_OFFSET32(stat_OutXonSent), - STATS_OFFSET32(stat_OutXoffSent), - STATS_OFFSET32(stat_MacControlFramesReceived), - STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), - STATS_OFFSET32(stat_IfInMBUFDiscards), + STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), + STATS_OFFSET32(stat_Dot3StatsFCSErrors), + STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), + STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), + STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), + STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), + STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), + STATS_OFFSET32(stat_Dot3StatsLateCollisions), + STATS_OFFSET32(stat_EtherStatsCollisions), + STATS_OFFSET32(stat_EtherStatsFragments), + STATS_OFFSET32(stat_EtherStatsJabbers), + STATS_OFFSET32(stat_EtherStatsUndersizePkts), + STATS_OFFSET32(stat_EtherStatsOverrsizePkts), + STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), + STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), + STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), + STATS_OFFSET32(stat_XonPauseFramesReceived), + STATS_OFFSET32(stat_XoffPauseFramesReceived), + STATS_OFFSET32(stat_OutXonSent), + STATS_OFFSET32(stat_OutXoffSent), + STATS_OFFSET32(stat_MacControlFramesReceived), + STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), + STATS_OFFSET32(stat_IfInMBUFDiscards), STATS_OFFSET32(stat_FwRxDrop), }; /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are * skipped because of errata. - */ + */ static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { 8,0,8,8,8,8,8,8,8,8, 4,0,4,4,4,4,4,4,4,4, @@ -5288,6 +5539,8 @@ memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); if (etest->flags & ETH_TEST_FL_OFFLINE) { + int i; + bnx2_netif_stop(bp); bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); bnx2_free_skbs(bp); @@ -5312,9 +5565,12 @@ } /* wait for link up */ - msleep_interruptible(3000); - if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG)) - msleep_interruptible(4000); + for (i = 0; i < 7; i++) { + if (bp->link_up) + break; + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(HZ); + } } if (bnx2_test_nvram(bp) != 0) { @@ -5420,7 +5676,8 @@ BNX2_EMAC_LED_TRAFFIC_OVERRIDE | BNX2_EMAC_LED_TRAFFIC); } - msleep_interruptible(500); + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(HZ / 2); if (signal_pending(current)) break; } @@ -5439,9 +5696,15 @@ .set_wol = bnx2_set_wol, .nway_reset = bnx2_nway_reset, .get_link = ethtool_op_get_link, +#if (LINUX_VERSION_CODE >= 0x20418) .get_eeprom_len = bnx2_get_eeprom_len, +#endif +#ifdef ETHTOOL_GEEPROM .get_eeprom = bnx2_get_eeprom, +#endif +#ifdef ETHTOOL_SEEPROM .set_eeprom = bnx2_set_eeprom, +#endif .get_coalesce = bnx2_get_coalesce, .set_coalesce = bnx2_set_coalesce, .get_ringparam = bnx2_get_ringparam, @@ -5451,7 +5714,9 @@ .get_rx_csum = bnx2_get_rx_csum, .set_rx_csum = bnx2_set_rx_csum, .get_tx_csum = ethtool_op_get_tx_csum, +#if (LINUX_VERSION_CODE >= 0x20418) .set_tx_csum = ethtool_op_set_tx_csum, +#endif .get_sg = ethtool_op_get_sg, .set_sg = ethtool_op_set_sg, #ifdef BCM_TSO @@ -5464,14 +5729,20 @@ .phys_id = bnx2_phys_id, .get_stats_count = bnx2_get_stats_count, .get_ethtool_stats = bnx2_get_ethtool_stats, +#ifdef ETHTOOL_GPERMADDR .get_perm_addr = ethtool_op_get_perm_addr, +#endif }; /* Called with rtnl_lock */ static int bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { +#if (LINUX_VERSION_CODE >= 0x020607) struct mii_ioctl_data *data = if_mii(ifr); +#else + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_ifru; +#endif struct bnx2 *bp = netdev_priv(dev); int err; @@ -5553,9 +5824,26 @@ { struct bnx2 *bp = netdev_priv(dev); - disable_irq(bp->pdev->irq); - bnx2_interrupt(bp->pdev->irq, dev, NULL); - enable_irq(bp->pdev->irq); +#if defined(RED_HAT_LINUX_KERNEL) && (LINUX_VERSION_CODE < 0x020600) + if (netdump_mode) { + bnx2_interrupt(bp->pdev->irq, dev, NULL); + if (dev->poll_list.prev) { + int budget = 64; + + bnx2_poll(dev, &budget); + } + } + else +#endif + { + disable_irq(bp->pdev->irq); +#if (LINUX_VERSION_CODE >= 0x20613) + bnx2_interrupt(bp->pdev->irq, dev); +#else + bnx2_interrupt(bp->pdev->irq, dev, NULL); +#endif + enable_irq(bp->pdev->irq); + } } #endif @@ -5566,9 +5854,12 @@ unsigned long mem_len; int rc; u32 reg; + u64 dma_mask, persist_dma_mask; SET_MODULE_OWNER(dev); +#if (LINUX_VERSION_CODE >= 0x20419) SET_NETDEV_DEV(dev, &pdev->dev); +#endif bp = netdev_priv(dev); bp->flags = 0; @@ -5611,26 +5902,15 @@ goto err_out_release; } - if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { - bp->flags |= USING_DAC_FLAG; - if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { - dev_err(&pdev->dev, - "pci_set_consistent_dma_mask failed, aborting.\n"); - rc = -EIO; - goto err_out_release; - } - } - else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { - dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); - rc = -EIO; - goto err_out_release; - } - bp->dev = dev; bp->pdev = pdev; spin_lock_init(&bp->phy_lock); +#if (LINUX_VERSION_CODE >= 0x20600) INIT_WORK(&bp->reset_task, bnx2_reset_task, bp); +#else + INIT_TQUEUE(&bp->reset_task, bnx2_reset_task, bp); +#endif dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); mem_len = MB_GET_CID_ADDR(17); @@ -5657,6 +5937,33 @@ bp->chip_id = REG_RD(bp, BNX2_MISC_ID); + /* 5708 cannot support DMA addresses > 40-bit. + * On 64-bit systems with IOMMU, use 40-bit dma_mask. + * On 64-bit systems without IOMMU, use 64-bit dma_mask and + * do DMA address check in bnx2_start_xmit(). + */ + if (CHIP_NUM(bp) == CHIP_NUM_5708) { + persist_dma_mask = dma_mask = DMA_40BIT_MASK; +#ifdef CONFIG_HIGHMEM + dma_mask = DMA_64BIT_MASK; +#endif + } else + persist_dma_mask = dma_mask = DMA_64BIT_MASK; + + /* Configure DMA attributes. */ + if (pci_set_dma_mask(pdev, dma_mask) == 0) { + dev->features |= NETIF_F_HIGHDMA; + rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask); + if (rc) { + dev_err(&pdev->dev, + "pci_set_consistent_dma_mask failed, aborting.\n"); + goto err_out_unmap; + } + } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) { + dev_err(&pdev->dev, "System does not support DMA, aborting.\n"); + goto err_out_unmap; + } + /* Get bus information. */ reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { @@ -5665,7 +5972,7 @@ bp->flags |= PCIX_FLAG; clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); - + clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; switch (clkreg) { case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: @@ -5762,7 +6069,7 @@ bp->tx_quick_cons_trip = 20; bp->tx_ticks_int = 80; bp->tx_ticks = 80; - + bp->rx_quick_cons_trip_int = 6; bp->rx_quick_cons_trip = 6; bp->rx_ticks_int = 18; @@ -5805,6 +6112,36 @@ bp->cmd_ticks_int = bp->cmd_ticks; } +#ifdef CONFIG_PCI_MSI + /* Disable MSI on 5706 if AMD 8132 bridge is found. + * + * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes + * with byte enables disabled on the unused 32-bit word. This is legal + * but causes problems on the AMD 8132 which will eventually stop + * responding after a while. + * + * AMD believes this incompatibility is unique to the 5706, and + * prefers to locally disable MSI rather than globally disabling it + * using pci_msi_quirk. + */ + if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) { + struct pci_dev *amd_8132 = NULL; + + while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8132_BRIDGE, + amd_8132))) { + u8 rev; + + pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev); + if (rev >= 0x10 && rev <= 0x13) { + disable_msi = 1; + pci_dev_put(amd_8132); + break; + } + } + } +#endif + bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; bp->req_line_speed = 0; if (bp->phy_flags & PHY_SERDES_FLAG) { @@ -5860,14 +6197,23 @@ printk(KERN_INFO "%s", version); /* dev zeroed in init_etherdev */ +#if (LINUX_VERSION_CODE >= 0x20418) dev = alloc_etherdev(sizeof(*bp)); +#else + dev = init_etherdev(NULL, sizeof(*bp)); +#endif if (!dev) return -ENOMEM; rc = bnx2_init_board(pdev, dev); if (rc < 0) { +#if (LINUX_VERSION_CODE >= 0x20418) free_netdev(dev); +#else + unregister_netdev(dev); + kfree(dev); +#endif return rc; } @@ -5895,6 +6241,23 @@ dev->poll_controller = poll_bnx2; #endif + pci_set_drvdata(pdev, dev); + + memcpy(dev->dev_addr, bp->mac_addr, 6); +#ifdef ETHTOOL_GPERMADDR + memcpy(dev->perm_addr, bp->mac_addr, 6); +#endif + bp->name = board_info[ent->driver_data].name; + + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; +#ifdef BCM_VLAN + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; +#endif +#ifdef BCM_TSO + dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; +#endif + +#if (LINUX_VERSION_CODE >= 0x20418) if ((rc = register_netdev(dev))) { dev_err(&pdev->dev, "Cannot register net device\n"); if (bp->regview) @@ -5905,12 +6268,7 @@ free_netdev(dev); return rc; } - - pci_set_drvdata(pdev, dev); - - memcpy(dev->dev_addr, bp->mac_addr, 6); - memcpy(dev->perm_addr, bp->mac_addr, 6); - bp->name = board_info[ent->driver_data].name, +#endif printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, " "IRQ %d, ", dev->name, @@ -5928,19 +6286,6 @@ printk("%2.2x", dev->dev_addr[i]); printk("\n"); - dev->features |= NETIF_F_SG; - if (bp->flags & USING_DAC_FLAG) - dev->features |= NETIF_F_HIGHDMA; - dev->features |= NETIF_F_IP_CSUM; -#ifdef BCM_VLAN - dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; -#endif -#ifdef BCM_TSO - dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN; -#endif - - netif_carrier_off(bp->dev); - return 0; } @@ -5950,14 +6295,20 @@ struct net_device *dev = pci_get_drvdata(pdev); struct bnx2 *bp = netdev_priv(dev); +#if (LINUX_VERSION_CODE >= 0x20600) flush_scheduled_work(); +#endif unregister_netdev(dev); if (bp->regview) iounmap(bp->regview); +#if (LINUX_VERSION_CODE >= 0x20418) free_netdev(dev); +#else + kfree(dev); +#endif pci_release_regions(pdev); pci_disable_device(pdev); pci_set_drvdata(pdev, NULL); @@ -5973,7 +6324,6 @@ if (!netif_running(dev)) return 0; - flush_scheduled_work(); bnx2_netif_stop(bp); netif_device_detach(dev); del_timer_sync(&bp->timer); @@ -5985,7 +6335,11 @@ reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; bnx2_reset_chip(bp, reset_code); bnx2_free_skbs(bp); +#if (LINUX_VERSION_CODE < 0x2060b) + bnx2_set_power_state(bp, state); +#else bnx2_set_power_state(bp, pci_choose_state(pdev, state)); +#endif return 0; } @@ -6016,7 +6370,11 @@ static int __init bnx2_init(void) { +#if (LINUX_VERSION_CODE < 0x020613) return pci_module_init(&bnx2_pci_driver); +#else + return pci_register_driver(&bnx2_pci_driver); +#endif } static void __exit bnx2_cleanup(void) diff -Naur linux-2.6.18/drivers/net/bnx2_fw.h linux-2.6.18.bnx2/drivers/net/bnx2_fw.h --- linux-2.6.18/drivers/net/bnx2_fw.h 2006-09-20 05:42:06.000000000 +0200 +++ linux-2.6.18.bnx2/drivers/net/bnx2_fw.h 2007-07-19 00:03:15.000000000 +0200 @@ -673,389 +673,698 @@ static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 }; static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; -static int bnx2_RXP_b06FwReleaseMajor = 0x1; -static int bnx2_RXP_b06FwReleaseMinor = 0x0; -static int bnx2_RXP_b06FwReleaseFix = 0x0; -static u32 bnx2_RXP_b06FwStartAddr = 0x08003184; -static u32 bnx2_RXP_b06FwTextAddr = 0x08000000; -static int bnx2_RXP_b06FwTextLen = 0x588c; -static u32 bnx2_RXP_b06FwDataAddr = 0x080058e0; -static int bnx2_RXP_b06FwDataLen = 0x0; -static u32 bnx2_RXP_b06FwRodataAddr = 0x08005890; -static int bnx2_RXP_b06FwRodataLen = 0x28; -static u32 bnx2_RXP_b06FwBssAddr = 0x08005900; -static int bnx2_RXP_b06FwBssLen = 0x13a4; -static u32 bnx2_RXP_b06FwSbssAddr = 0x080058e0; -static int bnx2_RXP_b06FwSbssLen = 0x1c; +static const int bnx2_RXP_b06FwReleaseMajor = 0x2; +static const int bnx2_RXP_b06FwReleaseMinor = 0x8; +static const int bnx2_RXP_b06FwReleaseFix = 0x17; +static const u32 bnx2_RXP_b06FwStartAddr = 0x08003184; +static const u32 bnx2_RXP_b06FwTextAddr = 0x08000000; +static const int bnx2_RXP_b06FwTextLen = 0x6728; +static const u32 bnx2_RXP_b06FwDataAddr = 0x080069c0; +static const int bnx2_RXP_b06FwDataLen = 0x0; +static const u32 bnx2_RXP_b06FwRodataAddr = 0x08006728; +static const int bnx2_RXP_b06FwRodataLen = 0x278; +static const u32 bnx2_RXP_b06FwBssAddr = 0x080069f0; +static const int bnx2_RXP_b06FwBssLen = 0x13dc; +static const u32 bnx2_RXP_b06FwSbssAddr = 0x080069c0; +static const int bnx2_RXP_b06FwSbssLen = 0x2c; static u8 bnx2_RXP_b06FwText[] = { - 0x1f, 0x8b, 0x08, 0x08, 0x07, 0x87, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, - 0x73, 0x74, 0x31, 0x2e, 0x62, 0x69, 0x6e, 0x00, 0xed, 0x5c, 0x5d, 0x6c, - 0x1c, 0xd7, 0x75, 0x3e, 0xf3, 0x43, 0x71, 0x49, 0x91, 0xd4, 0x70, 0xb9, - 0x62, 0x57, 0x12, 0x65, 0xed, 0x8a, 0x43, 0x71, 0x6d, 0x31, 0xce, 0x50, - 0x58, 0xdb, 0x82, 0xb1, 0x48, 0xc7, 0xb3, 0xa4, 0xc8, 0x24, 0x02, 0x42, - 0x1b, 0x42, 0xab, 0xa4, 0xa9, 0xc1, 0x90, 0x72, 0x91, 0x22, 0x2c, 0xa0, - 0x1a, 0x79, 0xf0, 0x43, 0x10, 0x2f, 0x56, 0x3f, 0xa6, 0xd1, 0x8d, 0x96, - 0xb6, 0x1c, 0x53, 0x08, 0x82, 0x82, 0xe5, 0x52, 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0xdc, 0xa3, 0xce, 0x01, 0x67, 0x3a, 0xc3, 0xfb, 0x05, + 0x94, 0x19, 0x1b, 0x99, 0xc3, 0x35, 0x16, 0xd4, 0xfd, 0x7c, 0x40, 0x73, + 0xf5, 0xf1, 0x87, 0xfd, 0x66, 0xaa, 0x56, 0x21, 0x13, 0xba, 0xab, 0x8c, + 0x9f, 0xad, 0x0f, 0x10, 0x73, 0x0f, 0xda, 0xfc, 0x45, 0xe4, 0x6f, 0xa6, + 0x8e, 0x29, 0x04, 0xcf, 0xf6, 0xc9, 0xb3, 0x26, 0x73, 0xcd, 0xd3, 0x6a, + 0xa2, 0xf2, 0x72, 0x90, 0x57, 0x7b, 0x57, 0x1d, 0xac, 0x35, 0x07, 0xfc, + 0xbc, 0x74, 0xbe, 0x7b, 0x6f, 0x2e, 0xfa, 0x5e, 0x39, 0x61, 0x4e, 0x7a, + 0x07, 0x78, 0xab, 0x36, 0x62, 0xd0, 0x41, 0xe0, 0x9d, 0xdd, 0xa6, 0xf5, + 0xb1, 0xd8, 0xf8, 0x97, 0xb7, 0xad, 0xf5, 0xb9, 0x15, 0x63, 0xb8, 0x35, + 0x40, 0xdf, 0x96, 0xb8, 0x71, 0xd1, 0x8f, 0x1b, 0x69, 0x1f, 0x1a, 0x58, + 0x81, 0x3a, 0xea, 0x2a, 0xf4, 0x64, 0xb7, 0x2d, 0xff, 0xfe, 0x03, 0x7d, + 0xe7, 0x95, 0xf0, 0x2c, 0x67, 0x00, 0x00, 0x00 }; static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; -static u32 bnx2_RXP_b06FwRodata[(0x28/4) + 1] = { - 0x0800468c, 0x0800458c, 0x08004630, 0x08004648, 0x08004660, 0x08004680, - 0x0800468c, 0x0800468c, 0x08004594, 0x00000000, 0x00000000 }; -static u32 bnx2_RXP_b06FwBss[(0x13a4/4) + 1] = { 0x0 }; -static u32 bnx2_RXP_b06FwSbss[(0x1c/4) + 1] = { 0x0 }; +static u32 bnx2_RXP_b06FwRodata[(0x278/4) + 1] = { + 0x08003fdc, 0x08003edc, 0x08003f80, 0x08003f98, 0x08003fb0, 0x08003fd0, + 0x08003fdc, 0x08003fdc, 0x08003ee4, 0x00000000, 0x08004a04, 0x08004a3c, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004a74, 0x08004c38, + 0x08004b80, 0x08004bb8, 0x08004c38, 0x08004b08, 0x08004c38, 0x08004c38, + 0x08004bb8, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004bf8, + 0x08004c38, 0x08004bf8, 0x08004b80, 0x08004c38, 0x08004c38, 0x08004bf8, + 0x08004bf8, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, 0x08004c38, + 0x08004ae4, 0x00000000, 0x08006018, 0x08006030, 0x08006030, 0x08006030, + 0x08006018, 0x08006030, 0x08006030, 0x08006030, 0x08006018, 0x08006030, + 0x08006030, 0x08006030, 0x08006018, 0x08006030, 0x08006030, 0x08006030, + 0x08006024, 0x00000000, 0x00000000 }; + +static u32 bnx2_RXP_b06FwBss[(0x13dc/4) + 1] = { 0x0 }; +static u32 bnx2_RXP_b06FwSbss[(0x2c/4) + 1] = { 0x0 }; static u8 bnx2_rv2p_proc1[] = { 0x1f, 0x8b, 0x08, 0x08, 0x5e, 0xd0, 0x41, 0x44, 0x00, 0x03, 0x74, 0x65, diff -Naur linux-2.6.18/drivers/net/bnx2.h linux-2.6.18.bnx2/drivers/net/bnx2.h --- linux-2.6.18/drivers/net/bnx2.h 2006-09-20 05:42:06.000000000 +0200 +++ linux-2.6.18.bnx2/drivers/net/bnx2.h 2007-07-19 00:03:16.000000000 +0200 @@ -13,6 +13,192 @@ #ifndef BNX2_H #define BNX2_H +#ifndef ADVERTISE_1000XFULL +#define ADVERTISE_1000XFULL 0x0020 +#define ADVERTISE_1000XHALF 0x0040 +#define ADVERTISE_1000XPAUSE 0x0080 +#define ADVERTISE_1000XPSE_ASYM 0x0100 +#endif + +#ifndef ADVERTISE_PAUSE_CAP +#define ADVERTISE_PAUSE_CAP 0x0400 +#define ADVERTISE_PAUSE_ASYM 0x0800 +#endif + +#ifndef MII_CTRL1000 +#define MII_CTRL1000 0x9 +#define MII_STAT1000 0xa +#endif + +#ifndef BMCR_SPEED1000 +#define BMCR_SPEED1000 0x0040 +#endif + +#ifndef ADVERTISE_1000FULL +#define ADVERTISE_1000FULL 0x0200 +#define ADVERTISE_1000HALF 0x0100 +#endif + +#ifndef SPEED_2500 +#define SPEED_2500 2500 +#endif + +#ifndef PCI_DEVICE_ID_NX2_5706 +#define PCI_DEVICE_ID_NX2_5706 0x164a +#define PCI_DEVICE_ID_NX2_5706S 0x16aa +#endif + +#ifndef PCI_DEVICE_ID_NX2_5708 +#define PCI_DEVICE_ID_NX2_5708 0x164c +#define PCI_DEVICE_ID_NX2_5708S 0x16ac +#endif + +#ifndef PCI_DEVICE_ID_AMD_8132_BRIDGE +#define PCI_DEVICE_ID_AMD_8132_BRIDGE 0x7458 +#endif + +#ifndef IRQ_RETVAL +typedef void irqreturn_t; +#define IRQ_RETVAL(x) +#define IRQ_HANDLED +#define IRQ_NONE +#endif + +#ifndef IRQF_SHARED +#define IRQF_SHARED SA_SHIRQ +#endif + +#ifndef NETDEV_TX_OK +#define NETDEV_TX_OK 0 +#endif + +#ifndef NETDEV_TX_BUSY +#define NETDEV_TX_BUSY 1 +#endif + +#if (LINUX_VERSION_CODE < 0x020547) +#define pci_set_consistent_dma_mask(pdev, mask) (0) +#endif + +#if (LINUX_VERSION_CODE < 0x020604) +#define MODULE_VERSION(version) +#endif + +#ifndef CHECKSUM_PARTIAL +#define CHECKSUM_PARTIAL CHECKSUM_HW +#endif + +#ifndef DMA_64BIT_MASK +#define DMA_64BIT_MASK ((u64) 0xffffffffffffffffULL) +#define DMA_32BIT_MASK ((u64) 0x00000000ffffffffULL) +#endif + +#ifndef DMA_40BIT_MASK +#define DMA_40BIT_MASK ((u64) 0x000000ffffffffffULL) +#endif + +#ifndef mmiowb +#define mmiowb() +#endif + +#if !defined(__iomem) +#define __iomem +#endif + +#if (LINUX_VERSION_CODE < 0x2060b) +typedef u32 pm_message_t; +typedef u32 pci_power_t; +#define PCI_D0 0 +#define PCI_D3hot 3 +#endif + +#if (LINUX_VERSION_CODE < 0x020605) +#define pci_dma_sync_single_for_cpu(pdev, map, len, dir) \ + pci_dma_sync_single(pdev, map, len, dir) + +#define pci_dma_sync_single_for_device(pdev, map, len, dir) +#endif + +#if (LINUX_VERSION_CODE < 0x020612) +static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev, + unsigned int length) +{ + struct sk_buff *skb = dev_alloc_skb(length); + if (skb) + skb->dev = dev; + return skb; +} + +static inline void netif_tx_lock(struct net_device *dev) +{ + spin_lock(&dev->xmit_lock); + dev->xmit_lock_owner = smp_processor_id(); +} + +static inline void netif_tx_unlock(struct net_device *dev) +{ + dev->xmit_lock_owner = -1; + spin_unlock(&dev->xmit_lock); +} + +#endif + +#if !defined(HAVE_NETDEV_PRIV) && (LINUX_VERSION_CODE != 0x020603) && (LINUX_VERSION_CODE != 0x020604) && (LINUX_VERSION_CODE != 0x20605) +static inline void *netdev_priv(struct net_device *dev) +{ + return dev->priv; +} +#endif + +#ifdef OLD_NETIF +static inline void netif_poll_disable(struct net_device *dev) +{ + while (test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state)) { + /* No hurry. */ + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(1); + } +} + +static inline void netif_poll_enable(struct net_device *dev) +{ + clear_bit(__LINK_STATE_RX_SCHED, &dev->state); +} + +static inline void netif_tx_disable(struct net_device *dev) +{ + spin_lock_bh(&dev->xmit_lock); + netif_stop_queue(dev); + spin_unlock_bh(&dev->xmit_lock); +} + +#endif + +#ifdef NETIF_F_TSO +#ifndef NETIF_F_GSO +static inline int skb_is_gso(const struct sk_buff *skb) +{ + return skb_shinfo(skb)->tso_size; +} +#define NETIF_F_TSO_ECN 0 +#define gso_size tso_size +#endif +#endif + +#if (LINUX_VERSION_CODE < 0x020600) +#define dev_err(unused, format, arg...) \ + printk(KERN_ERR "bnx2: " format , ## arg) +#else +#ifndef dev_err +#ifndef dev_printk +#define dev_printk(level, dev, format, arg...) \ + printk(level "bnx2 %s: " format , (dev)->bus_id , ## arg) +#endif +#define dev_err(dev, format, arg...) \ + dev_printk(KERN_ERR , dev , format , ## arg) +#endif +#endif + /* Hardware data structures and register definitions automatically * generated from RTL code. Do not modify. */ @@ -22,9 +208,9 @@ */ struct tx_bd { u32 tx_bd_haddr_hi; - u32 tx_bd_haddr_lo; - u32 tx_bd_mss_nbytes; - u32 tx_bd_vlan_tag_flags; + u32 tx_bd_haddr_lo; + u32 tx_bd_mss_nbytes; + u32 tx_bd_vlan_tag_flags; #define TX_BD_FLAGS_CONN_FAULT (1<<0) #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) #define TX_BD_FLAGS_IP_CKSUM (1<<2) @@ -3696,10 +3882,14 @@ /* 5708 Serdes PHY registers */ +#define BCM5708S_BMCR_FORCE_2500 0x20 + #define BCM5708S_UP1 0xb #define BCM5708S_UP1_2G5 0x1 +#define BCM5708S_1000X_STATUS2 0x15 + #define BCM5708S_BLK_ADDR 0x1f #define BCM5708S_BLK_ADDR_DIG 0x0000 @@ -3881,7 +4071,6 @@ #define PCI_32BIT_FLAG 2 #define ONE_TDMA_FLAG 4 /* no longer used */ #define NO_WOL_FLAG 8 -#define USING_DAC_FLAG 0x10 #define USING_MSI_FLAG 0x20 #define ASF_ENABLE_FLAG 0x40 @@ -3893,7 +4082,7 @@ u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES))); u16 hw_tx_cons; -#ifdef BCM_VLAN +#ifdef BCM_VLAN struct vlan_group *vlgrp; #endif @@ -3925,7 +4114,11 @@ int timer_interval; int current_interval; struct timer_list timer; +#if (LINUX_VERSION_CODE >= 0x020600) struct work_struct reset_task; +#else + struct tq_struct reset_task; +#endif int in_reset_task; /* Used to synchronize phy accesses. */ @@ -3950,7 +4143,7 @@ #define CHIP_REV_Ax 0x00000000 #define CHIP_REV_Bx 0x00001000 #define CHIP_REV_Cx 0x00002000 - + #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) #define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f) @@ -3969,7 +4162,7 @@ u32 phy_addr; u32 phy_id; - + u16 bus_speed_mhz; u8 wol; @@ -4025,7 +4218,7 @@ u32 advertising; - u8 req_flow_ctrl; /* flow ctrl advertisement */ + u8 req_flow_ctrl; /* flow ctrl advertisement */ /* settings or forced */ /* settings */ u8 autoneg; @@ -4038,6 +4231,7 @@ u8 serdes_an_pending; #define SERDES_AN_TIMEOUT (HZ / 3) +#define SERDES_FORCED_TIMEOUT (HZ / 10) u8 mac_addr[8]; @@ -4179,7 +4373,7 @@ #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000 #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000 #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000 - + #define BNX2_DRV_MSG_SEQ 0x0000ffff #define BNX2_FW_MB 0x00000008 @@ -4189,38 +4383,38 @@ #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 #define BNX2_LINK_STATUS 0x0000000c -#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff -#define BNX2_LINK_STATUS_LINK_UP 0x1 -#define BNX2_LINK_STATUS_LINK_DOWN 0x0 +#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff +#define BNX2_LINK_STATUS_LINK_UP 0x1 +#define BNX2_LINK_STATUS_LINK_DOWN 0x0 #define BNX2_LINK_STATUS_SPEED_MASK 0x1e -#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) -#define BNX2_LINK_STATUS_10HALF (1<<1) -#define BNX2_LINK_STATUS_10FULL (2<<1) -#define BNX2_LINK_STATUS_100HALF (3<<1) -#define BNX2_LINK_STATUS_100BASE_T4 (4<<1) -#define BNX2_LINK_STATUS_100FULL (5<<1) -#define BNX2_LINK_STATUS_1000HALF (6<<1) -#define BNX2_LINK_STATUS_1000FULL (7<<1) -#define BNX2_LINK_STATUS_2500HALF (8<<1) -#define BNX2_LINK_STATUS_2500FULL (9<<1) -#define BNX2_LINK_STATUS_AN_ENABLED (1<<5) -#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) -#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) -#define BNX2_LINK_STATUS_RESERVED (1<<8) -#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) -#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) -#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) -#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) -#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) -#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) -#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) -#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) -#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) -#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) -#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) -#define BNX2_LINK_STATUS_SERDES_LINK (1<<20) -#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) -#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) +#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) +#define BNX2_LINK_STATUS_10HALF (1<<1) +#define BNX2_LINK_STATUS_10FULL (2<<1) +#define BNX2_LINK_STATUS_100HALF (3<<1) +#define BNX2_LINK_STATUS_100BASE_T4 (4<<1) +#define BNX2_LINK_STATUS_100FULL (5<<1) +#define BNX2_LINK_STATUS_1000HALF (6<<1) +#define BNX2_LINK_STATUS_1000FULL (7<<1) +#define BNX2_LINK_STATUS_2500HALF (8<<1) +#define BNX2_LINK_STATUS_2500FULL (9<<1) +#define BNX2_LINK_STATUS_AN_ENABLED (1<<5) +#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) +#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) +#define BNX2_LINK_STATUS_RESERVED (1<<8) +#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) +#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) +#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) +#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) +#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) +#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) +#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) +#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) +#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) +#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) +#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) +#define BNX2_LINK_STATUS_SERDES_LINK (1<<20) +#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) +#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) #define BNX2_DRV_PULSE_MB 0x00000010 #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff @@ -4400,7 +4594,7 @@ 0x00020000) #define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \ 0x00030000) -#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE +#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_RESET) #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \ @@ -4443,7 +4637,7 @@ #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500) #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) - + #define BNX2_BC_STATE_DEBUG_CMD 0x1dc #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000