-- Structural VAMS generated by gnetlist -- Secondary unit ARCHITECTURE simple_arc OF BJT_transistor_simple IS terminal unnamed_net8 : electrical; terminal unnamed_net7 : electrical; terminal unnamed_net5 : electrical; terminal unnamed_net4 : electrical; terminal unnamed_net1 : electrical; BEGIN -- Architecture statement part SP1 : ENTITY SP_DIODE(SPICE_Diode_Model) GENERIC MAP ( VT => VT, AF => AF, KF => KF, PT => PT, EG => EG, M => ME, PB => PE, TT => TF, CJ0 => CJE, ISS => ISS) PORT MAP ( ANODE => unnamed_net8, KATHODE => unnamed_net5); CS2 : ENTITY SPICE_cs(current_controlled) GENERIC MAP ( N => BF, VT => VT, ISS => ISS) PORT MAP ( urt => unnamed_net4, lrt => unnamed_net5, ult => unnamed_net1, llt => unnamed_net8); CAP2 : ENTITY CAPACITOR PORT MAP ( LT => unnamed_net5, RT => unnamed_net1); CAP1 : ENTITY CAPACITOR PORT MAP ( LT => unnamed_net1, RT => unnamed_net4); GND1 : ENTITY GROUND_NODE PORT MAP ( T1 => unnamed_net7); CAP3 : ENTITY CAPACITOR GENERIC MAP ( c => CCS) PORT MAP ( LT => unnamed_net7, RT => unnamed_net4); RES_emitter : ENTITY RESISTOR GENERIC MAP ( r => RE) PORT MAP ( RT => unnamed_net5, LT => emitter); RES_collector : ENTITY RESISTOR GENERIC MAP ( r => RC) PORT MAP ( RT => collector, LT => unnamed_net4); RES_base : ENTITY RESISTOR GENERIC MAP ( r => RB) PORT MAP ( RT => unnamed_net1, LT => base); END ARCHITECTURE simple_arc;