This is "Digital Gate Compiler" (DGC).
A system for the creation of digital circuits.
Overview
--------
Digital circuits can be used to build some kind of hardware.
Often a hardware is an application specific integrated circuit
or a programmable logic array. In this both cases hardware is
created from a 'netlist'. Such a netlist contains information
about the connection of some basic building blocks (gates).
DGC is a system for the creation of netlist files by using an
abstract spezification of digital systems.
The following types of specification are supported:
- PLA (Sum of product expression)
- BEX (Boolean expression)
- NEX (Numeric expression)
- KISS (State machine description)
- BMS (Burst mode specification, Subset of state machine description)
- DGD (Script language to build hierarchical designs)
For the conversion from an abstract description to a netlist,
DGC needs to know what kind of basic building blocks are available.
Such a file is called a gate library.
| EXAMPLE:
| After installing DGC, binaries are installed at:
| <installation-path>/bin
| Additional example files are stored at:
| <installation-path>/share/dgc
| Example files are called "example.<ext>". To test your installation
| you could simply call
| <installation-path>/bin/dgc example.pla
Input Files
-----------
This is a list of currently supported input formats:
PLA (.pla, .pl)
This is a sum of product representation of several
boolean functions. This format is used in the well known
espresso tool (University of California).
http://www-cad.eecs.berkeley.edu/Software/software.html
BEX (.bex, boolean expression)
This is a more readable format for boolean functions.
See example.bex for a description.
NEX (.nex, numeric expression)
Extracts boolean functions from mathematical expressions.
See example.nex for a description.
KISS (.kiss)
A description of a finite state machine. This file format
is used by the tools KISS, NOVA and others. Some of these
tooles can be found in the SIS package
http://www-cad.eecs.berkeley.edu/Software/software.html
The file example.kiss can be found in
<installation-path>/share/dgc
BMS (.bms, burst mode spezification)
Also a file format for the description of finite state machines.
It is a spezial restricted format to describe asynchronous
state machines. A description of the format is included
in the MINIMALIST package (Columbia University)
http://www.cs.columbia.edu/async/
DGD (.dgd, digital gate design)
This is a small script language to import and use all supported
file formats. See the file
<installation-path>/share/dgc/d_latch.dgd
for an example.
Gate Library Files
------------------
GENLIB (.genlib)
The GENLIB library format is also part of the sis package.
A description can be found in the 'sis/genlib' subdirectory of sis.
The download location for 'sis' is:
http://www-cad.eecs.berkeley.edu/Software/software.html
Synopsys Library Source (.lib)
DGC supports a subset of the Synopsys Gate Library source code language.
It does NOT support synopsys compiled libraries.
Binary DGC Library (.dgl)
The internal compiled library format. This format is generated by
the library compiler 'dglc'.
Output Files
------------
EDIF (.edif)
The elecronic design interchange format (http://www.edif.org/).
This is the most used and known format to store a netlist.
VHDL-netlist (.vhdl)
VHDL can be used to store a netlist. This format has been added
to support simulation of the result with a digital VHDL simulator.
XNF (.xnf)
There is an experimental Xilinx netlist export filter.
(ftp://ftp.xilinx.com/pub/documentation/xactstep6/00_index.htm)
| EXAMPLE:
| These output files are generated by the tool 'dgc' in
| <installation-path>/bin
| The output format is specified by one of the output options.
| To generate an EDIF netlist, use the following statement:
| dgc example.pl -oe netlist.edif
Tools
-----
dgc [Compiler]
The main tool of the package. It creates a netlist from the
specified input file.
Input files: All above (automatic detection)
Supported library formats: All above
Supported output formats: All above
| EXAMPLE:
| The example file
| <installation-path>/share/dgc/example.kiss
| is a simple finite state machine. Calling 'dgc' with
| dgc -lib min.genlib -rsl example.kiss -ov netlist.vhdl
| Creates a VHDL netlist with a low active reset signal for
| the state machine. 'dgc' uses only gates from the file
| 'min.genlib'.
dglc [Library Compiler]
Converts one or more library files into the internal binary format.
Input files: All supported library formats (automatic detection).
simfsm
A program to generate support files for fsm simulation. Its main
purpose is to generate stimuli data for finite state machines.
At the moment, only VHDL is supported.
bms2kiss
Convert a BMS description into the corresponding KISS description.
Input file: BMS
Output file: KISS
dgsop [Sum of Product Minimizer]
The dgc package contains many functions for 2-level minimization.
This tool gives access to some of these functions. The idea
of this tool is to provide a clone of the program 'espresso'.
Input file: PLA, BEX, NEX
Output file: PLA, stdout
| EXAMPLE:
| The example file
| <installation-path>/share/dgc/example.nex
| describes the product of two 3-bit values. The command
| dgsop example.nex
| reads the file, buildes all boolean functions and does a
| minimization of these functions.
| Using
| dgsop -nop example.nex
| would convert 'example.nex' to a PLA format and write the result
| to stdout.
Technical Background
--------------------
Most algorithms for digital minimization and synthesis
are taken from:
Giovanni DeMicheli
Synthesis and Optimization of Digital Circuits, 1994
McGraw-Hill Book Company, Inc.
ISBN 0-07-113271-6
For some additional proofs and descriptions, the following
book might be useful:
Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen and
Alberto L. Sangiovanni-Vincentelli
Logic Minimization Algorithms for VLSI Synthesis, 1994
Kluwer Academic Publishers Group
ISBN 0-8983-164-9
More general algorithms such as shortest path or the
greedy altorithm are described in:
Thomas H. Cormen, Charles E. Leiserson and Ronald L. Rivest
Introduction to Algorithms, 1993
ISBN 0-262-03141-8
Oliver Kraus
olikraus@yahoo.com
