# Alliance CAD System
# Copyright (C) 1990-2004 ASIM/LIP6/UPMC
#
# Home page : http://asim.lip6.fr/recherche/alliance/
# E-mail : mailto:alliance-users@asim.lip6.fr
# ftp site : ftp://asim.lip6.fr/pub/alliance/
#
This document lists the main differences between each Alliance's revisions.
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ALLIANCE revision 5.0 (2004/09/09)
- Many Bugs fix in Loon and Boog, Graal, etc ...
+ Bug fix in AP parser when using a SCALE_X > 100 (integer overflow)
+ Bug fix and improvements of Ramlib and Rf2lib cells
+ Bug fix in Graal for segment edition with a scale != 1
+ Bug fix in Loon (critical path delay computation)
+ Bug fix in Loon (xsch driver crash)
+ ...
- Minor Sxlib cells modifications to match 0.13 micron techno rules
+ see www.vlsitechnology.org for details
- Graal improvements and new features :
+ fractional values (min segment width) are now supported in the .graal file
+ fractional values are now supported for segment/connector/transistors width
+ full working edition on a grid < 1 lambda
- LAX format new feature :
+ Delays and capacitances can now be specified usign floating point values.
- VASY new feature :
+ It accepts now 'after clauses' in concurrent signal assignements.
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ALLIANCE revision 5.0 (2004/07/31)
- Many bugs have been fixed in tool such as : VASY, Loon, Boog, OCR, LVX,
Spice driver or VST parser/driver etc ...
- All the 50 tools have been ported to Cygwin and graphical tools such as
Graal and Dreal are now fully/really working (no more bug with
Dialog boxes using Lesstif !)
- New tool : Mips_asm to convert MIPS ASM to VHDL ROM description
(used with the MIPS circuit example)
- All tutorials have been rewritten/updated
- Man pages have been updated
- More than 15 New complete circuit examples from VHDL up to layout
including a makefile to generate each of them automatically !
This set of circuits include a MIPS R3000 ...
- A new autoconf/automake directory structure, much more convenient
and faster than before.
- A new HTML documentation describing each tool and Alliance file
formats used all over the design flow.
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ALLIANCE revision 5.0 (2002/05/03)
1/ Large changes in the sources
- Alliance now build with gnu autoconf/automake
- Alliance's C Libraries aren't numbered anymore
(ie libMut.a rather than libMut315.a...)
2/ New tools
- nero replaces ocr.
- dpgen is now integrated into genlib.
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ALLIANCE revision 4.9.0 (2002/02/14)
1/ New tools
Place and Route:
ocp and ocr replace scr.
2/ This is pre-release 5.0 version.
We have decided to remove in Alliance 5.0 all tools, libs, cell
libs and documentation wich doesn't work or are obsolete :
removed tools:
ali algue amg bbr bop bsg c4map dlx_asm dlx_asm_v0_2 dpr fpgen fpmap
genscan genview genview_cc1 genview_cpp genview_gcc glop grog k2f l2p
mips_asm obsolete_bop obsolete_genscan obsolete_glop obsolete_scmap pocpag
rage rfg rsa scmap scr sicc xvpn
removed cells:
amg bsg dplib fplib grog padlib rage rf2lib rfg rflib rsa sc2sxlib sclib
3/ Renamed tools
lynx is renamed cougar
ali is renamed ale
This is to avoid name clash with well known internet tools
(btw: we had the anteriority of the name lynx...)
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ALLIANCE revision 4.5.0 (2001/10/11)
1/ New tools
Datapath:
dpgen replaces fpgen and dpr is dead
Synthesys :
boom replaces bop
boog replaces scmap
loon replaces glop
scanpath:
scapin replace genscan
2/ AP and AL format :
new layers, new transistors
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ALLIANCE revision 4.0.9 (2001/02/21)
1/ SXlib (man sxlib)
is now the default standard cells library. sclib will be thrown away
some day...
2/ New Tools for place and route with silicon ensemble : (to replace scr)
a2def
a2lef
def2a
sea
seplace
seroute
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ALLIANCE release 4.0.6 (01/02/2000)
1/ Public release
2/ Fixed some Y2K small bugs
- Dates on Alliance's parser/driver are in now the form : "dd/mm/YYYY"
- Dates on Compass's parser/driver are in now the form : "dd-MON-YYYY"
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ALLIANCE revision 4.0 (15/10/99)
1/ New Standard Cells Library : sxlib
sxlib allows multi-layer over cell routing
and all transitions are now on rising edge (man sxlib)
2/ Improved Tools :
- asimut is now a temporal logic simulator.
You *must* modify your old pattern files to allow delays (man asimut)
- syf can now handle vbe statements in .fsm
- dreal : New viewing options ( like -install for private colormap)
- graal : New viewing options ( like -install for private colormap)
Input scale changeable, Hierarchy browser, real view (.cif/.gds)
3/ New Tools :
algue : ALliance Graphic User Environment
ali : gives information on Alliance Environment
b2f : FSM Abstraction from .vbe
k2f : Translate kiss2 format <-> FSM format
vasy : Translate .vhd format (Synopsys) <-> .vbe format
xsch : Netlist viewer
xfsm : FSM viewer
xpat : patterns (with delay) viewer
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ALLIANCE revision 3.5 (19/06/98)
1/ Lots of improvements and bug fixes
2/ AP : Now supports ten layers of metal
3/ AL : New support for RC net in losig. Parsers al, spice, vti modified.
Modified Data Structures :
- lotrs : added field BULK TRNAME
- locon : added field PNODE
- losig : added field PRCN, CAPA deleted
Modified functions (the CAPA field has moved) :
addlosig, addlotrs, dellosig
4/ RCN : New library for RC support : Resistances on losig and capcitances
between losig.
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ALLIANCE revision 3.2c (20/03/98)
1/ Ap format :
Alliance ap format now supports
- half grid spacing
- connectors somewhere else than abutment box.
2/ VERILOG driver :
Support added for Alliance-Cadence Toolbox
3/ MBK_SCALE_X now defaults to 100
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ALLIANCE release 3.2b (15/12/97)
1/ Easy install
A "configure" script is now available to configure
Alliance on any UNIX system
2/ New driver :
Support to VERILOG netlist as been added.
Only driver exits. This means you can save your
netlists to VERILOG format 'vlg'
3/ New names :
- Logic has been splited in 3 parts,
. bop : boolean optimizer (logic -o)
. scmap : Std cell mapping (logic -s)
. c4map : CCCC mapping (logic -c)
- Desb is replaced by yagle
- Alligator is replaced by fpmap (X4000)
- Netoptim is replaced glop
4/ Cells libraries
The tree of directories containing the cells
libraries has been simplified
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ALLIANCE revision 3.2 (17/05/97)
1/ GRAPHICAL PATTERN VIEWER
In order to see the patterns resulting from a simulation,
the XPAT tools has been developed.
2/ GRAPHICAL FSM VIEWER
In order to see the state's graph of an FSM the XFSM tools has
been developed.
3/ RECTANGLE LAYOUT VIEWER
Now, DREAL is also a real layout editor.
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ALLIANCE release 3.0 (17/05/94)
1/ FPGA SYNTHESIS
A logic synthesis tools that maps on FPGA is now available.
It works for X3000 devices
2/ FLOOR-PLAN ROUTING
Binaries of the CHEOPS router from BULL are available for sparc.
3/ TIMING ANALYSIS
The static timing analysis tools TAS is finally available.
It can be targeted to several processes though the use of a technological
file suffixed `elp'.
4/ RECTANGLE LAYOUT VIEWER
In order to see the layout resulting from a symbolic to real translation,
the DREAL tools has been developed.
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ALLIANCE release 2.0 (14/02/94) versus ALLIANCE 1.2
1/ SYMBOLIC LAYOUT EDITOR
The symbolic layout editor ALC has been replaced by GRAAL.
GRAAL provides the same functionalities than ALC, but is much
more reliable. GRAAL support both CMOS and GaAs symbolic layout.
> man graal
2/ DESIGN RULE CHECKER
The Design Rule Checker VERSATIL has been replaced by DRUC.
DRUC provides the same functionnalities than VERSATIL.
A hierarchical version will be distributed in the next ALLIANCE release.
> man druc
3/ LOGIC SYNTHESIS
The logic synthesis tool LOGIC has been strongly improved.
The new tool NETOPTIM is a gate-level net-list optimizer
that allows to minimize delays in a synthesized gate net-list.
The Finite-state-machine synthesizer SYF allows to describe and
synthesize high complexity FSM (more than 100 states)
It is possible to describe hierarchical FSM using stack (subroutines).
> man logic
> man syf
> man netoptim
4/ DATA-PATH COMPILER
FPGEN is a data-path compiler using a dedicated macro-cells library.
DPR is the place and route tool that creates optimized data-path blocks
from the gate net-list generated by FPGEN.
> man fpgen
> man dpr
5/ PARAMETERIZED MACRO-CELLS
Six parameterized generators are part of this release:
> man rsa # fast adder generator
> man bsg # barrel shifter generator
> man amg # multiplier generator
> man rfg # register file generator
> man grog # high speed ROM generator
> man rage # static RAM generator
6/ PROCEDURAL LAYOUT DEBUGGER
The graphic debugger GENVIEW allows to debug custom blocks
described with the procedural language GENLIB.
It makes possible to design new parameterized generators, using the
GENLIB language.
> man genview
7/ POSTSCIPT DRIVER
The postscript driver MBK2PS has been replaced by L2P, in order to
obtain a printable postscript file from a cell layout.
This tool accept not only symbolic layout (.ap files) but also
physical layout (.cif or .gds files).
> man l2p
8/ FLOOR-PLAN ROUTER
There is no floor-plan router in this release.
If you need to interconnect two blocks, you can use the BBR tool
that is actually a simple gridless channel router.
> man bbr
9/ FILE FORMATS
Both file formats .ap (symbolic layout) and .al (net-list)
have been modified, with upward compatibility: all files
created with ALLIANCE release 1.2 are readable and usable with
ALLIANCE release 2.0.
> man ap
> man al
10/ PROCESS MAPPING
The S2R tool that performs the physical mapping to a target process
has been documented: the procedure to parameterize the technology
file is described in the doc/misc/process_mapping.ps file.
The technology file format has been modified.
> man s2r
> man prol
# EOF
