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ghc-ghc-devel-6.12.3-8.6.fc14.i686.rpm

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>RegAlloc.Linear.Base</TITLE
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>ghc-6.12.3: The GHC API</TD
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><A HREF="index.html"
>Contents</A
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>RegAlloc.Linear.Base</FONT
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><TD CLASS="s15"
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><TR
><TD CLASS="section1"
>Description</TD
></TR
><TR
><TD CLASS="doc"
>Put common type definitions here to break recursive module dependencies.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Synopsis</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>type</SPAN
> <A HREF="#t%3ABlockAssignment"
>BlockAssignment</A
> = <A HREF="RegAlloc-Liveness.html#t%3ABlockMap"
>BlockMap</A
> (<A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
>, <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
>)</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ALoc"
>Loc</A
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
>= <A HREF="#v%3AInReg"
>InReg</A
> !<A HREF="Reg.html#t%3ARealReg"
>RealReg</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3AInMem"
>InMem</A
> !<A HREF="RegAlloc-Linear-StackMap.html#t%3AStackSlot"
>StackSlot</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3AInBoth"
>InBoth</A
> !<A HREF="Reg.html#t%3ARealReg"
>RealReg</A
> !<A HREF="RegAlloc-Linear-StackMap.html#t%3AStackSlot"
>StackSlot</A
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AregsOfLoc"
>regsOfLoc</A
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
> -&gt; [<A HREF="Reg.html#t%3ARealReg"
>RealReg</A
>]</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ASpillReason"
>SpillReason</A
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
>= <A HREF="#v%3ASpillAlloc"
>SpillAlloc</A
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3ASpillClobber"
>SpillClobber</A
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3ASpillLoad"
>SpillLoad</A
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3ASpillJoinRR"
>SpillJoinRR</A
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3ASpillJoinRM"
>SpillJoinRM</A
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ARegAllocStats"
>RegAllocStats</A
>  = <A HREF="#v%3ARegAllocStats"
>RegAllocStats</A
> {<TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_spillInstrs"
>ra_spillInstrs</A
> :: <A HREF="UniqFM.html#t%3AUniqFM"
>UniqFM</A
> [<A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
>]</TD
></TR
></TABLE
>}</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ARA_State"
>RA_State</A
>  = <A HREF="#v%3ARA_State"
>RA_State</A
> {<TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_blockassig"
>ra_blockassig</A
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_freeregs"
>ra_freeregs</A
> :: !<A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_assig"
>ra_assig</A
> :: <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_delta"
>ra_delta</A
> :: <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_stack"
>ra_stack</A
> :: <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_us"
>ra_us</A
> :: <A HREF="UniqSupply.html#t%3AUniqSupply"
>UniqSupply</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_spills"
>ra_spills</A
> :: [<A HREF="RegAlloc-Linear-Base.html#t%3ASpillReason"
>SpillReason</A
>]</TD
></TR
></TABLE
>}</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>newtype</SPAN
>  <A HREF="#t%3ARegM"
>RegM</A
> a = <A HREF="#v%3ARegM"
>RegM</A
> {<TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="recfield"
><A HREF="#v%3AunReg"
>unReg</A
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ARA_State"
>RA_State</A
> -&gt; (#<A HREF="RegAlloc-Linear-Base.html#t%3ARA_State"
>RA_State</A
>, a#)</TD
></TR
></TABLE
>}</TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Documentation</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>type</SPAN
> <A NAME="t:BlockAssignment"
><A NAME="t%3ABlockAssignment"
></A
></A
><B
>BlockAssignment</B
> = <A HREF="RegAlloc-Liveness.html#t%3ABlockMap"
>BlockMap</A
> (<A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
>, <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
>)</TD
></TR
><TR
><TD CLASS="doc"
>Used to store the register assignment on entry to a basic block.
	We use this to handle join points, where multiple branch instructions
	target a particular label. We have to insert fixup code to make
	the register assignments from the different sources match up.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:Loc"
><A NAME="t%3ALoc"
></A
></A
><B
>Loc</B
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Where a vreg is currently stored
	A temporary can be marked as living in both a register and memory
	(InBoth), for example if it was recently loaded from a spill location.
	This makes it cheap to spill (no save instruction required), but we
	have to be careful to turn this into InReg if the value in the
	register is changed.
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:InReg"
><A NAME="v%3AInReg"
></A
></A
><B
>InReg</B
> !<A HREF="Reg.html#t%3ARealReg"
>RealReg</A
></TD
><TD CLASS="rdoc"
>vreg is in a register
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:InMem"
><A NAME="v%3AInMem"
></A
></A
><B
>InMem</B
> !<A HREF="RegAlloc-Linear-StackMap.html#t%3AStackSlot"
>StackSlot</A
></TD
><TD CLASS="rdoc"
>vreg is held in a stack slot
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:InBoth"
><A NAME="v%3AInBoth"
></A
></A
><B
>InBoth</B
> !<A HREF="Reg.html#t%3ARealReg"
>RealReg</A
> !<A HREF="RegAlloc-Linear-StackMap.html#t%3AStackSlot"
>StackSlot</A
></TD
><TD CLASS="rdoc"
>vreg is held in both a register and a stack slot
</TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:Loc')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:Loc" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="../base-4.2.0.2/Data-Eq.html#t%3AEq"
>Eq</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="../base-4.2.0.2/Data-Ord.html#t%3AOrd"
>Ord</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="../base-4.2.0.2/Text-Show.html#t%3AShow"
>Show</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="Outputable.html#t%3AOutputable"
>Outputable</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:regsOfLoc"
><A NAME="v%3AregsOfLoc"
></A
></A
><B
>regsOfLoc</B
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
> -&gt; [<A HREF="Reg.html#t%3ARealReg"
>RealReg</A
>]</TD
></TR
><TR
><TD CLASS="doc"
>Get the reg numbers stored in this Loc.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:SpillReason"
><A NAME="t%3ASpillReason"
></A
></A
><B
>SpillReason</B
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Reasons why instructions might be inserted by the spiller.
	Used when generating stats for -ddrop-asm-stats.
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:SpillAlloc"
><A NAME="v%3ASpillAlloc"
></A
></A
><B
>SpillAlloc</B
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
><TD CLASS="rdoc"
>vreg was spilled to a slot so we could use its
	current hreg for another vreg
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:SpillClobber"
><A NAME="v%3ASpillClobber"
></A
></A
><B
>SpillClobber</B
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
><TD CLASS="rdoc"
>vreg was moved because its hreg was clobbered
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:SpillLoad"
><A NAME="v%3ASpillLoad"
></A
></A
><B
>SpillLoad</B
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
><TD CLASS="rdoc"
>vreg was loaded from a spill slot
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:SpillJoinRR"
><A NAME="v%3ASpillJoinRR"
></A
></A
><B
>SpillJoinRR</B
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
><TD CLASS="rdoc"
>reg-reg move inserted during join to targets
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:SpillJoinRM"
><A NAME="v%3ASpillJoinRM"
></A
></A
><B
>SpillJoinRM</B
> !<A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
><TD CLASS="rdoc"
>reg-mem move inserted during join to targets
</TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:RegAllocStats"
><A NAME="t%3ARegAllocStats"
></A
></A
><B
>RegAllocStats</B
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Used to carry interesting stats out of the register allocator.
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="5" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:RegAllocStats"
><A NAME="v%3ARegAllocStats"
></A
></A
><B
>RegAllocStats</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="body" COLSPAN="2"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:ra_spillInstrs"
><A NAME="v%3Ara_spillInstrs"
></A
></A
><B
>ra_spillInstrs</B
> :: <A HREF="UniqFM.html#t%3AUniqFM"
>UniqFM</A
> [<A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
>]</TD
><TD CLASS="rdoc"
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:RA_State"
><A NAME="t%3ARA_State"
></A
></A
><B
>RA_State</B
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>The register alloctor state
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="5" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:RA_State"
><A NAME="v%3ARA_State"
></A
></A
><B
>RA_State</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="body" COLSPAN="2"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:ra_blockassig"
><A NAME="v%3Ara_blockassig"
></A
></A
><B
>ra_blockassig</B
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
></TD
><TD CLASS="rdoc"
>the current mapping from basic blocks to 
 	the register assignments at the beginning of that block.
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_freeregs"
><A NAME="v%3Ara_freeregs"
></A
></A
><B
>ra_freeregs</B
> :: !<A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
></TD
><TD CLASS="rdoc"
>free machine registers
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_assig"
><A NAME="v%3Ara_assig"
></A
></A
><B
>ra_assig</B
> :: <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
><TD CLASS="rdoc"
>assignment of temps to locations
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_delta"
><A NAME="v%3Ara_delta"
></A
></A
><B
>ra_delta</B
> :: <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>current stack delta
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_stack"
><A NAME="v%3Ara_stack"
></A
></A
><B
>ra_stack</B
> :: <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
></TD
><TD CLASS="rdoc"
>free stack slots for spilling
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_us"
><A NAME="v%3Ara_us"
></A
></A
><B
>ra_us</B
> :: <A HREF="UniqSupply.html#t%3AUniqSupply"
>UniqSupply</A
></TD
><TD CLASS="rdoc"
>unique supply for generating names for join point fixup blocks.
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_spills"
><A NAME="v%3Ara_spills"
></A
></A
><B
>ra_spills</B
> :: [<A HREF="RegAlloc-Linear-Base.html#t%3ASpillReason"
>SpillReason</A
>]</TD
><TD CLASS="rdoc"
>Record why things were spilled, for -ddrop-asm-stats.
 	Just keep a list here instead of a map of regs -&gt; reasons.
 	We don't want to slow down the allocator if we're not going to emit the stats.
</TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>newtype</SPAN
>  <A NAME="t:RegM"
><A NAME="t%3ARegM"
></A
></A
><B
>RegM</B
> a </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>The register allocator monad type.
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="5" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:RegM"
><A NAME="v%3ARegM"
></A
></A
><B
>RegM</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="body" COLSPAN="2"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:unReg"
><A NAME="v%3AunReg"
></A
></A
><B
>unReg</B
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ARA_State"
>RA_State</A
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