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ghc-ghc-devel-6.12.3-8.6.fc14.i686.rpm

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>RegAlloc.Linear.State</TITLE
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>ghc-6.12.3: The GHC API</TD
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><A HREF="index.html"
>Contents</A
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>Index</A
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><FONT SIZE="6"
>RegAlloc.Linear.State</FONT
></TD
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></TABLE
></TD
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><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Description</TD
></TR
><TR
><TD CLASS="doc"
>State monad for the linear register allocator.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Synopsis</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ARA_State"
>RA_State</A
>  = <A HREF="#v%3ARA_State"
>RA_State</A
> {<TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_blockassig"
>ra_blockassig</A
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_freeregs"
>ra_freeregs</A
> :: !<A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_assig"
>ra_assig</A
> :: <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_delta"
>ra_delta</A
> :: <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_stack"
>ra_stack</A
> :: <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_us"
>ra_us</A
> :: <A HREF="UniqSupply.html#t%3AUniqSupply"
>UniqSupply</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3Ara_spills"
>ra_spills</A
> :: [<A HREF="RegAlloc-Linear-Base.html#t%3ASpillReason"
>SpillReason</A
>]</TD
></TR
></TABLE
>}</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3ARegM"
>RegM</A
> a</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3ArunR"
>runR</A
> ::  <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
> -&gt; <A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
> -&gt; <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
> -&gt; <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
> -&gt; <A HREF="UniqSupply.html#t%3AUniqSupply"
>UniqSupply</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> a -&gt; (<A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
>, <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
>, <A HREF="RegAlloc-Linear-Base.html#t%3ARegAllocStats"
>RegAllocStats</A
>, a)</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AspillR"
>spillR</A
> :: <A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> instr =&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="Unique.html#t%3AUnique"
>Unique</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> (instr, <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
>)</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AloadR"
>loadR</A
> :: <A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> instr =&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> instr</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AgetFreeRegsR"
>getFreeRegsR</A
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AsetFreeRegsR"
>setFreeRegsR</A
> :: <A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AgetAssigR"
>getAssigR</A
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> (<A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
>)</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AsetAssigR"
>setAssigR</A
> :: <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AgetBlockAssigR"
>getBlockAssigR</A
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AsetBlockAssigR"
>setBlockAssigR</A
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AsetDeltaR"
>setDeltaR</A
> :: <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AgetDeltaR"
>getDeltaR</A
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AgetUniqueR"
>getUniqueR</A
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3ArecordSpill"
>recordSpill</A
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ASpillReason"
>SpillReason</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Documentation</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:RA_State"
><A NAME="t%3ARA_State"
></A
></A
><B
>RA_State</B
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>The register alloctor state
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="5" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:RA_State"
><A NAME="v%3ARA_State"
></A
></A
><B
>RA_State</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="body" COLSPAN="2"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:ra_blockassig"
><A NAME="v%3Ara_blockassig"
></A
></A
><B
>ra_blockassig</B
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
></TD
><TD CLASS="rdoc"
>the current mapping from basic blocks to 
 	the register assignments at the beginning of that block.
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_freeregs"
><A NAME="v%3Ara_freeregs"
></A
></A
><B
>ra_freeregs</B
> :: !<A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
></TD
><TD CLASS="rdoc"
>free machine registers
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_assig"
><A NAME="v%3Ara_assig"
></A
></A
><B
>ra_assig</B
> :: <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
></TD
><TD CLASS="rdoc"
>assignment of temps to locations
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_delta"
><A NAME="v%3Ara_delta"
></A
></A
><B
>ra_delta</B
> :: <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>current stack delta
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_stack"
><A NAME="v%3Ara_stack"
></A
></A
><B
>ra_stack</B
> :: <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
></TD
><TD CLASS="rdoc"
>free stack slots for spilling
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_us"
><A NAME="v%3Ara_us"
></A
></A
><B
>ra_us</B
> :: <A HREF="UniqSupply.html#t%3AUniqSupply"
>UniqSupply</A
></TD
><TD CLASS="rdoc"
>unique supply for generating names for join point fixup blocks.
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:ra_spills"
><A NAME="v%3Ara_spills"
></A
></A
><B
>ra_spills</B
> :: [<A HREF="RegAlloc-Linear-Base.html#t%3ASpillReason"
>SpillReason</A
>]</TD
><TD CLASS="rdoc"
>Record why things were spilled, for -ddrop-asm-stats.
 	Just keep a list here instead of a map of regs -&gt; reasons.
 	We don't want to slow down the allocator if we're not going to emit the stats.
</TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:RegM"
><A NAME="t%3ARegM"
></A
></A
><B
>RegM</B
> a </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>The register allocator monad type.
</TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:RegM')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:RegM" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="../base-4.2.0.2/Control-Monad.html#t%3AMonad"
>Monad</A
> <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:runR"
><A NAME="v%3ArunR"
></A
></A
><B
>runR</B
> ::  <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
> -&gt; <A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
> -&gt; <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
> -&gt; <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
> -&gt; <A HREF="UniqSupply.html#t%3AUniqSupply"
>UniqSupply</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> a -&gt; (<A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
>, <A HREF="RegAlloc-Linear-StackMap.html#t%3AStackMap"
>StackMap</A
>, <A HREF="RegAlloc-Linear-Base.html#t%3ARegAllocStats"
>RegAllocStats</A
>, a)</TD
></TR
><TR
><TD CLASS="doc"
>Run a computation in the RegM register allocator monad.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:spillR"
><A NAME="v%3AspillR"
></A
></A
><B
>spillR</B
> :: <A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> instr =&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="Unique.html#t%3AUnique"
>Unique</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> (instr, <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
>)</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:loadR"
><A NAME="v%3AloadR"
></A
></A
><B
>loadR</B
> :: <A HREF="Instruction.html#t%3AInstruction"
>Instruction</A
> instr =&gt; <A HREF="Reg.html#t%3AReg"
>Reg</A
> -&gt; <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> instr</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:getFreeRegsR"
><A NAME="v%3AgetFreeRegsR"
></A
></A
><B
>getFreeRegsR</B
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:setFreeRegsR"
><A NAME="v%3AsetFreeRegsR"
></A
></A
><B
>setFreeRegsR</B
> :: <A HREF="RegAlloc-Linear-X86-FreeRegs.html#t%3AFreeRegs"
>FreeRegs</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:getAssigR"
><A NAME="v%3AgetAssigR"
></A
></A
><B
>getAssigR</B
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> (<A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
>)</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:setAssigR"
><A NAME="v%3AsetAssigR"
></A
></A
><B
>setAssigR</B
> :: <A HREF="RegAlloc-Liveness.html#t%3ARegMap"
>RegMap</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ALoc"
>Loc</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:getBlockAssigR"
><A NAME="v%3AgetBlockAssigR"
></A
></A
><B
>getBlockAssigR</B
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:setBlockAssigR"
><A NAME="v%3AsetBlockAssigR"
></A
></A
><B
>setBlockAssigR</B
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ABlockAssignment"
>BlockAssignment</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:setDeltaR"
><A NAME="v%3AsetDeltaR"
></A
></A
><B
>setDeltaR</B
> :: <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:getDeltaR"
><A NAME="v%3AgetDeltaR"
></A
></A
><B
>getDeltaR</B
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:getUniqueR"
><A NAME="v%3AgetUniqueR"
></A
></A
><B
>getUniqueR</B
> :: <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="Unique.html#t%3AUnique"
>Unique</A
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="decl"
><A NAME="v:recordSpill"
><A NAME="v%3ArecordSpill"
></A
></A
><B
>recordSpill</B
> :: <A HREF="RegAlloc-Linear-Base.html#t%3ASpillReason"
>SpillReason</A
> -&gt; <A HREF="RegAlloc-Linear-State.html#t%3ARegM"
>RegM</A
> <A HREF="../ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="doc"
>Record that a spill instruction was inserted, for profiling.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="botbar"
>Produced by <A HREF="http://www.haskell.org/haddock/"
>Haddock</A
> version 2.6.1</TD
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