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>ghc-6.12.3: The GHC API</TD
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>SPARC.AddrMode</FONT
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>Synopsis</TD
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><TD CLASS="decl"
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>data</SPAN
> <A HREF="#t%3AAddrMode"
>AddrMode</A
> </TD
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>= <A HREF="#v%3AAddrRegReg"
>AddrRegReg</A
> <A HREF="Reg.html#t%3AReg"
>Reg</A
> <A HREF="Reg.html#t%3AReg"
>Reg</A
></TD
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><TD CLASS="decl"
>| <A HREF="#v%3AAddrRegImm"
>AddrRegImm</A
> <A HREF="Reg.html#t%3AReg"
>Reg</A
> <A HREF="SPARC-Imm.html#t%3AImm"
>Imm</A
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><TD CLASS="decl"
><A HREF="#v%3AaddrOffset"
>addrOffset</A
> :: <A HREF="SPARC-AddrMode.html#t%3AAddrMode"
>AddrMode</A
> -> <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -> <A HREF="../base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="SPARC-AddrMode.html#t%3AAddrMode"
>AddrMode</A
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>Documentation</TD
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><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
> <A NAME="t:AddrMode"
><A NAME="t%3AAddrMode"
></A
></A
><B
>AddrMode</B
> </TD
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>Represents a memory address in an instruction.
Being a RISC machine, the SPARC addressing modes are very regular.
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>Constructors</TD
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><TD CLASS="arg"
><A NAME="v:AddrRegReg"
><A NAME="v%3AAddrRegReg"
></A
></A
><B
>AddrRegReg</B
> <A HREF="Reg.html#t%3AReg"
>Reg</A
> <A HREF="Reg.html#t%3AReg"
>Reg</A
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:AddrRegImm"
><A NAME="v%3AAddrRegImm"
></A
></A
><B
>AddrRegImm</B
> <A HREF="Reg.html#t%3AReg"
>Reg</A
> <A HREF="SPARC-Imm.html#t%3AImm"
>Imm</A
></TD
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></TD
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><TD CLASS="decl"
><A NAME="v:addrOffset"
><A NAME="v%3AaddrOffset"
></A
></A
><B
>addrOffset</B
> :: <A HREF="SPARC-AddrMode.html#t%3AAddrMode"
>AddrMode</A
> -> <A HREF="../base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -> <A HREF="../base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="SPARC-AddrMode.html#t%3AAddrMode"
>AddrMode</A
></TD
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>Add an integer offset to the address in an AddrMode.
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