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<h1>usrp2::usrp2 Member List</h1> </div>
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This is the complete list of members for <a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a>, including all inherited members.<table>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a49bc0d8a533ad7259e5574acfd027d68">adc_rate</a>(long *rate)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aa1e646a4b9695438a3175eb1c3b7a324">burn_mac_addr</a>(const std::string &new_addr)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a5a547f128bb1129445e90f029c36d63c">config_mimo</a>(int flags)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac1e9dd22b54da3bd44fa6d46b43293b8">dac_rate</a>(long *rate)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a4cf2cc57c170200e09b45da8f82b990b">default_tx_scale_iq</a>(int interpolation_factor, int *scale_i, int *scale_q)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#acf667cea17739ba8b8ede8cf162a7272">enable_gpio_streaming</a>(int bank, int enable)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a91771bfb13bb9e7e7534310204b9192e">fpga_master_clock_freq</a>(long *freq)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#adaf0f547244415fc982a7b177358ca11">interface_name</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a94b9b36e7740874af7fae96198bbbb46">mac_addr</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aca00b5a1e9ff0b801e321bd6a3250d92">make</a>(const std::string &ifc, const std::string &addr="", size_t rx_bufsize=0)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a0e992c0ab2d8b0c8a99723ed9fe55d2e">MAX_CHAN</a></td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a3d89fc2845a564ab3b3077699f434e1a">peek32</a>(uint32_t addr, uint32_t words)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a8f386b5781d5a675eaa647cc0b2c54fe">poke32</a>(uint32_t addr, const std::vector< uint32_t > &data)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aef356a85afe76aa2938b022b73c38ddd">read_gpio</a>(int bank, uint16_t *value)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#acd497e686236e986d2a7c9708101fc94">rx_daughterboard_id</a>(int *dbid)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a67b1f9df5af54a95db4e68adb85d53c3">rx_decim</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac0bbc275573f647df2d898051fe60e8a">rx_freq_max</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a1acb81b5b6bcff145ab35be1c72d5114">rx_freq_min</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a48a79f89af26ef21cfdb168527946b0b">rx_gain_db_per_step</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ae371035411d10fab287fbcdac98ff5f5">rx_gain_max</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac75be9cf7591eb34ee20a9c8a2bb7737">rx_gain_min</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a4586604bf3d2614e5d7533e22549aaa9">rx_missing</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a268b49a605a2cc001e753052b91367a1">rx_overruns</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#adc5c23804bb1277b89ec51c519275c42">rx_samples</a>(unsigned int channel, rx_sample_handler *handler)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aee3d2e654c22198430c7626ee65676e1">set_gpio_ddr</a>(int bank, uint16_t value, uint16_t mask)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#af2893ac8a6f56e62b05fc486740ffacb">set_gpio_sels</a>(int bank, std::string sels)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a64706690819e7d25c85a3c2bb3171100">set_rx_center_freq</a>(double frequency, tune_result *result)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a0e4330e851a12f2de3044a9abeb5125f">set_rx_decim</a>(int decimation_factor)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac2726fe4d9071afeb5fde690d31fe7bc">set_rx_gain</a>(double gain)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a26ca99959366c7d2ceba3df8435a89e5">set_rx_lo_offset</a>(double frequency)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac77b97e74940641d531f204422656ea3">set_rx_scale_iq</a>(int scale_i, int scale_q)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a187858c2d829c319f44a1e3db6ca38d8">set_tx_center_freq</a>(double frequency, tune_result *result)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a8f3512a284bcdb566e9f33d2b58eec7c">set_tx_gain</a>(double gain)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a97a89168fa7801f6681c499210cc08f3">set_tx_interp</a>(int interpolation_factor)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aca5cd4b1f1943c17b93e664c441d7126">set_tx_lo_offset</a>(double frequency)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aa458137a015f61fb400e626b594e2852">set_tx_scale_iq</a>(int scale_i, int scale_q)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a495be65b27a7096b8de897b0a033c3ab">sptr</a> typedef</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a99811f59a38aa3097e0be6196cf3790a">start_rx_streaming</a>(unsigned int channel=0, unsigned int items_per_frame=0)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a75c9dc7c14da792f8fb6a73b8caaabb1">stop_rx_streaming</a>(unsigned int channel=0)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac57859c598d0b2f7fec17731fdf1f333">sync_every_pps</a>(bool enable)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a6407149eaf9535bac0642889d0c67a6f">sync_to_pps</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aa90bd651ad3c2750dccff12444b48282">tx_16sc</a>(unsigned int channel, const std::complex< int16_t > *samples, size_t nsamples, const tx_metadata *metadata)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a6a11fb6a5567d69e584cf16b02e510ca">tx_32fc</a>(unsigned int channel, const std::complex< float > *samples, size_t nsamples, const tx_metadata *metadata)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#aef3c674c9f2c7495e197a5c6130a2cce">tx_daughterboard_id</a>(int *dbid)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a21a76cc4ab69185d796bf5602c9cb8ff">tx_freq_max</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a23803477520e7d6a470c445c70a2c60b">tx_freq_min</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a17abc39bc29e3d1d13e7d8082e1e577a">tx_gain_db_per_step</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#abfd17a980f1450e4c6cb9bfb9a54d413">tx_gain_max</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a0534b619c93788c66686268983da34c7">tx_gain_min</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#afcd40f8eb490f95f3b88e403beb95db7">tx_interp</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a9853a8439165f467814d472024c4c551">tx_raw</a>(unsigned int channel, const uint32_t *items, size_t nitems, const tx_metadata *metadata)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#ac4f19c8609dfde67d0b1cfbb80f9d90c">write_gpio</a>(int bank, uint16_t value, uint16_t mask)</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp2_1_1usrp2.html#a40577de9cf7226d231e048bd8f66cbec">~usrp2</a>()</td><td><a class="el" href="classusrp2_1_1usrp2.html">usrp2::usrp2</a></td><td></td></tr>
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