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<h1>usrp_standard_rx Member List</h1> </div>
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This is the complete list of members for <a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a>, including all inherited members.<table>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a09ce78134eea035e42464123356096e4">_common_write_oe</a>(txrx_t txrx, int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a3814dc28edce07e3b5cb48bb3ebdf244">_read_9862</a>(int which_codec, int regno, unsigned char *value) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad28278c9ff7a33b3a151c561ab037b9f">_read_9862</a>(int which_codec, int regno) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a8f92d2e9630ec614eedc61858756cce1">_read_aux_adc</a>(int slot, int which_adc, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a2aadef5c105459794b22a135730e7480">_read_aux_adc</a>(int slot, int which_adc)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a4fa26bd8164bd5782adf7fbe00b3d411">_read_fpga_reg</a>(int regno, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#abf1f167a1c96dd0ed4589afc6c9fad6c">_read_fpga_reg</a>(int regno)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a9b54622fec87c2ed9c7808078931371f">_read_spi</a>(int optional_header, int enables, int format, int len)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a4585f9c7df7084a6acb29bd6d7950892">_set_led</a>(int which_led, bool on)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a8a25444c83f59f7517d0ff687d2ff053">_write_9862</a>(int which_codec, int regno, unsigned char value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab8870a35e0bdc63ee6655b5264a6d142">_write_aux_dac</a>(int slot, int which_dac, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac5bdb9be69f27eb3a0530cba9536d0f4">_write_fpga_reg</a>(int regno, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a0c200dc2d39d68d7a77e92859c5228a0">_write_fpga_reg_masked</a>(int regno, int value, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a83f39a101787d86a0850e72499286c00">_write_oe</a>(int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aaf100fafc406ef75faafcf3e38df7849">_write_spi</a>(int optional_header, int enables, int format, std::string buf)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#ace4aa6537246ecf948ec0ae35e1d6e48">adc_rate</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#ab42bca6a45be1e18e074b494905db7db">block_size</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a9452b1ce5881965ca36d780f928b6cb6">calc_dxc_freq</a>(double target_freq, double baseband_freq, double fs, double *dxc_freq, bool *inverted)</td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac25d56e74572309a87397f0fce1a102b">common_pga</a>(txrx_t txrx, int which_amp) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a06cfd0e5675618f773c5466bd235a369">common_pga_db_per_step</a>(txrx_t txrx) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a7dd5c384b9d2cd4e412939c3b7b7ac79">common_pga_max</a>(txrx_t txrx) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a95453e5bb4d0ed4c05b1ea64c880170a">common_pga_min</a>(txrx_t txrx) const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a37bd03473a98cf3776f1988914c1a5ce">common_read_aux_adc</a>(txrx_t txrx, int which_side, int which_adc, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab84d66e92dc16fdc104fae9341f1e64f">common_read_aux_adc</a>(txrx_t txrx, int which_side, int which_adc)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#af7e33b5762cd9c80a714806fa6fa2244">common_read_io</a>(txrx_t txrx, int which_side, int *value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a217f6865ef04d1111c2c1d3e7b4260f5">common_read_io</a>(txrx_t txrx, int which_side)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a52f96a90c91ed6e74bfc6a91691a7fa2">common_set_pga</a>(txrx_t txrx, int which_amp, double gain_in_db)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a0997e93568c71e5432c2445b1ebcc991">common_write_atr_mask</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a89eda6a96bc7f4d2d634da793eccbc20">common_write_atr_rxval</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a26e38a0f9f98390b712709812e3387af">common_write_atr_txval</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ac7354a9c4f7e961cb1b541c970a8d009">common_write_aux_dac</a>(txrx_t txrx, int which_side, int which_dac, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#acf3120592af4df79d38d253c98c633ae">common_write_io</a>(txrx_t txrx, int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad673bc49b311e29ab01727c5933ea028">common_write_refclk</a>(txrx_t txrx, int which_side, int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#afd14b376f2449cfb71865c9980ea2358">converter_rate</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [inline, virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a1d6b6839b9ba385d93684c3497c3fb16">d_bytes_per_poll</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aa45df525ed16ee0c885a4972ac7908b4">d_db</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a686ea66e3f43c9ab6df60bd80f41ac3b">d_dbid</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#afa81d2ee842dd6eef04c422276f52d1d">d_fpga_master_clock_freq</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#af3d08c8bcdd0ed116e76ffa5449004f2">d_fpga_shadows</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a10536cd0fe631c3a1084c0404873ad5b">d_udh</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a4e5297f0010c8f39cfe4fff838b113a4">d_usb_data_rate</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a6d0fecbe64f35fef20293c27dc33a0b0">d_verbose</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a34128f4864ece7fafc011786c42b9994">daughterboard_id</a>(int which_side) const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [inline, virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a8eb1f58ca819437d7f43ad87574bd6da">db</a>() const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a9e3dfe1821b5aa2438a014fd7ca579f4">db</a>(int which_side)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#ab92676b3ff5e472846e957f95c3374e5">decim_rate</a>() const </td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a1b1d513ec9017203d3d2eede645093d5">determine_rx_mux_value</a>(const usrp_subdev_spec &ss)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#abfe3924bcd4da66e431bac0d20a99bf4">determine_rx_mux_value</a>(const usrp_subdev_spec &ss_a, const usrp_subdev_spec &ss_b)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#aec8c94d230440bb38951e9718755b994">disable_rx</a>()</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a138542206516dba75c5c90af984dcf84">format</a>() const </td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a8bc4f06d059eff8bc6bc3766d89b5d41">format_bypass_halfband</a>(unsigned int format)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a15cc1572f31cd9b0436dbc4aaad4b634">format_shift</a>(unsigned int format)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#ad5f82de396844f5e1864b6602f3f1066">format_want_q</a>(unsigned int format)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a7e7b2474c65673c9a68dfc8f08293399">format_width</a>(unsigned int format)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a244d4aa01bb6a054cd5bd0998ce2a09a">fpga_master_clock_freq</a>() const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a745ee8680106fee8e3937019e48c0c41a5749d17a9377d91ea89fc6b8f94620b9">FPGA_MODE_COUNTING</a> enum value</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a745ee8680106fee8e3937019e48c0c41a26cf58fafbdee14b54d0eef63660332e">FPGA_MODE_COUNTING_32BIT</a> enum value</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a745ee8680106fee8e3937019e48c0c41adc8004f6da0507be39531d73039011f8">FPGA_MODE_LOOPBACK</a> enum value</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a745ee8680106fee8e3937019e48c0c41ad3f99a72b4201bac21d8c103eff81568">FPGA_MODE_NORMAL</a> enum value</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#ac259e77beebe73376a45b6116ab845e1">has_rx_halfband</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a4192e505766a5920f8771bde1fd871ae">has_tx_halfband</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a9d4d1ef184ad622c7f84a6f940614b9b">init_db</a>(usrp_basic_sptr u)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a61af504df443a9d846ecf909871f1481">is_valid</a>(const usrp_subdev_spec &ss)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a988775e6036abf58339c689d94b3bcf5">make</a>(int which_board, unsigned int decim_rate, int nchan=1, int mux=-1, int mode=0, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a81f51a370ce934e853969e487e2214df">usrp_basic_rx::make</a>(int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#ae77c37e8be21095bb6add76e1c261121">make_format</a>(int width=16, int shift=0, bool want_q=true, bool bypass_halfband=false)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ae9277f41b745b1c96c422804fafd058a">MAX_REGS</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected, static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a5705205822065977c5e777aafe5c203f">mux</a>() const </td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a0ad5d52ec8a7c7270e6248614ae0a4a4">nchannels</a>() const </td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a07b889dbe4fecd870f40ddf2401948c6">nddcs</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a9dec671bc0d7c50157083f46538844af">nducs</a>() const </td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a982d36d1f8d64a5bb2604cf04caa22d4">pga</a>(int which_amp) const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a7c570ad5c2cb879f1b9f2073117ecf51">pga_db_per_step</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a2089bd929d76f28a620fc66726b525f4">pga_max</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a984a57196c26958e2927667ab3abe4cf">pga_min</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a9edf0c0a2aeab58f7f12483a02dd14ee">probe_rx_slots</a>(bool verbose)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#ac339662f98db1292b636baf9f2db3d0a">read</a>(void *buf, int len, bool *overrun)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#acffe1b022ad3ba669ab2131896ebafbf">read_aux_adc</a>(int which_side, int which_adc, int *value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#aedc2bc043ad6fed139274328a39a11be">read_aux_adc</a>(int which_side, int which_adc)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#aefe7a2f10626831304091babff21dc0d">read_eeprom</a>(int i2c_addr, int eeprom_offset, int len)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a364d3e56a0749a90cc5de2ac378e6863">READ_FAILED</a></td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [static]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab284caa2e15464f62aa80ad1f540ecc5">read_i2c</a>(int i2c_addr, int len)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a275d14df1506faa570fd5cc231a14ee9">read_io</a>(int which_side, int *value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a67b0c263712cd5bd56f48e6bd8754bc6">read_io</a>(int which_side)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a15a44f86a1a019e94d18f3c19b4cd34a">restore_rx</a>(bool on)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#aa25e7e0e84ec50bd8689889401480f84">rx_enable</a>() const </td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [inline, protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a1b8044ecae8a8acc9bb84e40dce4076e">rx_freq</a>(int channel) const </td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a648de1479d7632b59bf2732f231ddbe0">selected_subdev</a>(const usrp_subdev_spec &ss)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a70a71308412a67eaf825c13399faa078">serial_number</a>()</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a97fc801cbafa85040a3d39be03d27a62">set_adc_buffer_bypass</a>(int which_adc, bool bypass)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad0e07c8d85aa220aaf150e27dd8b545f">set_adc_offset</a>(int which_adc, int offset)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab18f4a02c0efcac10f8e9406ca7a57a7">set_dac_offset</a>(int which_dac, int offset, int offset_pin)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#af20cc324fca8d089226d5a6dfc3d3668">set_dc_offset_cl_enable</a>(int bits, int mask)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a71a1352e5b799f798ea528a09f240b7d">set_ddc_phase</a>(int channel, int phase)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#af75a82a32f50117b4acfe518b0c31e89">set_decim_rate</a>(unsigned int rate)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#ad196898bb518333f3ce753905d3cfd0a">set_format</a>(unsigned int format)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a825640d1de15253b5bae18762a0e403e">set_fpga_master_clock_freq</a>(long master_clock)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#aafcd5898e3cddfaacd0535a6a678aafd">set_fpga_mode</a>(int mode)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#aba133cd0d5c853a51beb96776e7030fc">set_fpga_rx_sample_rate_divisor</a>(unsigned int div)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#aa98b7831a644635f19ee84a7ecd404b2">set_mux</a>(int mux)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a9ab9aa92005647b967d063003a841ca0">set_nchannels</a>(int nchannels)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a85804ff6612a34c800a7181ea90de6b4">set_pga</a>(int which_amp, double gain_in_db)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a14fa02bdeea1bc11d5611b879dae5405">set_rx_enable</a>(bool on)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a4f3584afcc01962580cf420015d93cda">set_rx_freq</a>(int channel, double freq)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a77535750946e7d8443a76941a9611cae">set_usb_data_rate</a>(int usb_data_rate)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ae200e6eb7dbbaf81a3c1353a401f97d3">set_verbose</a>(bool on)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#afaae41796f1468062d4ad237322baf9e">shutdown_daughterboards</a>()</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#ac97772bce1c0aaca0fee2462accd8123">start</a>()</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a545808dbbdc7de3331123e7af6021144">stop</a>()</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a261d53e643bfc5e6bdaa2f84a070bd42">tune</a>(int chan, db_base_sptr db, double target_freq, usrp_tune_result *result)</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a530c23ff633c630530ec491c368a755d">usb_data_rate</a>() const </td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [inline]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ab81b0e66f94e4b4310925eab149ffdea">usrp_basic</a>(int which_board, struct usb_dev_handle *open_interface(struct usb_device *dev), const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#acbda9587edf161df5aa2c504e42096ff">usrp_basic_rx</a>(int which_board, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__common.html#a084f39cd160734d41e6c1cb8f6513dd6">usrp_standard_common</a>(usrp_basic *parent)</td><td><a class="el" href="classusrp__standard__common.html">usrp_standard_common</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#acf2afdc165b27469cc8f793851c78a3c">usrp_standard_rx</a>(int which_board, unsigned int decim_rate, int nchan=1, int mux=-1, int mode=0, int fusb_block_size=0, int fusb_nblocks=0, const std::string fpga_filename="", const std::string firmware_filename="")</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a0974bedf9b0406709e83e839f40e2b36">write_atr_mask</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#ad9b95b1ca0e2616c1b3808892fdda1b0">write_atr_rx_delay</a>(int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a7cb8b45ce6815d3ee3c97a064a63e9ee">write_atr_rxval</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a70f4070830b0db3fd0c3addb97ce966e">write_atr_tx_delay</a>(int value)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a914e9b61a4b1441dc955b1dc9cd17742">write_atr_txval</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#ae5cbeedfd6df52cdc4b13c87e2521b97">write_aux_dac</a>(int which_side, int which_dac, int value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a3900d37e951b83c938669f5fa0255866">write_eeprom</a>(int i2c_addr, int eeprom_offset, const std::string buf)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a182048083827bf3e2efddb918677e51e">write_hw_mux_reg</a>()</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td><code> [protected]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a664e5aa3a3fb8a4c50b752906fcb79a0">write_i2c</a>(int i2c_addr, const std::string buf)</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#a5ab1edec410f1d5399c187cb243905a5">write_io</a>(int which_side, int value, int mask)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#ac6c7387f1bf488ee22c79be22e3f48dd">write_refclk</a>(int which_side, int value)</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic.html#a01313a5f1c8e0eea1a1ff26388e25f78">~usrp_basic</a>()</td><td><a class="el" href="classusrp__basic.html">usrp_basic</a></td><td><code> [virtual]</code></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__basic__rx.html#ae50eef2481209ecaa7eb73bfd0cb513d">~usrp_basic_rx</a>()</td><td><a class="el" href="classusrp__basic__rx.html">usrp_basic_rx</a></td><td></td></tr>
<tr class="memlist"><td><a class="el" href="classusrp__standard__rx.html#a51b7fde714bddf8bc2352172f07f42df">~usrp_standard_rx</a>()</td><td><a class="el" href="classusrp__standard__rx.html">usrp_standard_rx</a></td><td></td></tr>
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