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ghc-ForSyDe-devel-3.1.1-4.fc14.i686.rpm

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><TD CLASS="title"
>ForSyDe-3.1.1: ForSyDe's Haskell-embedded Domain Specific Language.</TD
><TD CLASS="topbut"
><A HREF="src/ForSyDe-Backend-VHDL.html"
>Source code</A
></TD
><TD CLASS="topbut"
><A HREF="index.html"
>Contents</A
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>Index</A
></TD
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><TD CLASS="modulebar"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
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><TD
><FONT SIZE="6"
>ForSyDe.Backend.VHDL</FONT
></TD
><TD ALIGN="right"
><TABLE CLASS="narrow" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="infohead"
>Portability</TD
><TD CLASS="infoval"
>portable</TD
></TR
><TR
><TD CLASS="infohead"
>Stability</TD
><TD CLASS="infoval"
>experimental</TD
></TR
><TR
><TD CLASS="infohead"
>Maintainer</TD
><TD CLASS="infoval"
>forsyde-dev@ict.kth.se</TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Description</TD
></TR
><TR
><TD CLASS="doc"
>This module provides the VHDL backend of ForSyDe's embedded compiler
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Synopsis</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="#v%3AwriteVHDL"
>writeVHDL</A
> ::  <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> a -&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/System-IO.html#t%3AIO"
>IO</A
> <A HREF="/usr/share/doc/ghc/html/libraries/ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AwriteVHDLOps"
>writeVHDLOps</A
> ::  <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
> -&gt; <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> a -&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/System-IO.html#t%3AIO"
>IO</A
> <A HREF="/usr/share/doc/ghc/html/libraries/ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AwriteAndModelsimVHDL"
>writeAndModelsimVHDL</A
> :: <A HREF="ForSyDe-System.html#t%3ASysFunToIOSimFun"
>SysFunToIOSimFun</A
> sysF simF =&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> sysF -&gt; simF</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AwriteAndModelsimVHDLOps"
>writeAndModelsimVHDLOps</A
> :: <A HREF="ForSyDe-System.html#t%3ASysFunToIOSimFun"
>SysFunToIOSimFun</A
> sysF simF =&gt; <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
> -&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> sysF -&gt; simF</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3AVHDLOps"
>VHDLOps</A
>  = <A HREF="#v%3AVHDLOps"
>VHDLOps</A
> {<TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="recfield"
><A HREF="#v%3AdebugVHDL"
>debugVHDL</A
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLDebugLevel"
>VHDLDebugLevel</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3ArecursivityVHDL"
>recursivityVHDL</A
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLRecursivity"
>VHDLRecursivity</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3AexecQuartus"
>execQuartus</A
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusOps"
>QuartusOps</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3AcompileModelsim"
>compileModelsim</A
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Bool.html#t%3ABool"
>Bool</A
></TD
></TR
></TABLE
>}</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3AQuartusOps"
>QuartusOps</A
>  = <A HREF="#v%3AQuartusOps"
>QuartusOps</A
> {<TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="recfield"
><A HREF="#v%3Aaction"
>action</A
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusAction"
>QuartusAction</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3AfMax"
>fMax</A
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3AfpgaFamiliyDevice"
>fpgaFamiliyDevice</A
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> (<A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>, <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>)</TD
></TR
><TR
><TD CLASS="recfield"
><A HREF="#v%3ApinAssigs"
>pinAssigs</A
> :: [(<A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>, <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>)]</TD
></TR
></TABLE
>}</TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3AQuartusAction"
>QuartusAction</A
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
>= <A HREF="#v%3AAnalysisAndElaboration"
>AnalysisAndElaboration</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3AAnalysisAndSynthesis"
>AnalysisAndSynthesis</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3AFullCompilation"
>FullCompilation</A
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AcheckSynthesisQuartus"
>checkSynthesisQuartus</A
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusOps"
>QuartusOps</A
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3AVHDLDebugLevel"
>VHDLDebugLevel</A
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
>= <A HREF="#v%3AVHDLNormal"
>VHDLNormal</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3AVHDLVerbose"
>VHDLVerbose</A
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
><SPAN CLASS="keyword"
>data</SPAN
>  <A HREF="#t%3AVHDLRecursivity"
>VHDLRecursivity</A
>  </TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="decl"
>= <A HREF="#v%3AVHDLRecursive"
>VHDLRecursive</A
></TD
></TR
><TR
><TD CLASS="decl"
>| <A HREF="#v%3AVHDLNonRecursive"
>VHDLNonRecursive</A
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s8"
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="#v%3AdefaultVHDLOps"
>defaultVHDLOps</A
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="section1"
>Documentation</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:writeVHDL"
><A NAME="v%3AwriteVHDL"
></A
></A
><B
>writeVHDL</B
> ::  <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> a -&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/System-IO.html#t%3AIO"
>IO</A
> <A HREF="/usr/share/doc/ghc/html/libraries/ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL.html#writeVHDL"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Given a System Definition whose name is a valid VHDL _basic_ identifier 
   (call it &quot;A&quot;) generate <TT
>A.vhd</TT
> in current working directory using 
   default compilation options.
   Imp: the input and output signal names of A must be valid VHDL identifiers
        (basic or extended) and different to <TT
>clk</TT
> and <TT
>reset</TT
>
        which are reserved for the main clock and reset signals
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:writeVHDLOps"
><A NAME="v%3AwriteVHDLOps"
></A
></A
><B
>writeVHDLOps</B
> ::  <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
> -&gt; <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> a -&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/System-IO.html#t%3AIO"
>IO</A
> <A HREF="/usr/share/doc/ghc/html/libraries/ghc-prim-0.2.0.0/GHC-Unit.html#t%3A%28%29"
>()</A
></TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL.html#writeVHDLOps"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
><TT
><A HREF="ForSyDe-Backend-VHDL.html#v%3AwriteVHDL"
>writeVHDL</A
></TT
>-alternative which allows setting VHDL compilation options.
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:writeAndModelsimVHDL"
><A NAME="v%3AwriteAndModelsimVHDL"
></A
></A
><B
>writeAndModelsimVHDL</B
></TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL.html#writeAndModelsimVHDL"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="arg"
>:: <A HREF="ForSyDe-System.html#t%3ASysFunToIOSimFun"
>SysFunToIOSimFun</A
> sysF simF</TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
>=&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
>Number of cycles to simulate
   if <TT
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#v%3ANothing"
>Nothing</A
></TT
> the number will be determined
   by the length of the input stimulti.
   Useful when the system to simulate doesn't
   have inputs or the inputs provided are 
   infinite
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> sysF</TD
><TD CLASS="rdoc"
>system definition to simulate
</TD
></TR
><TR
><TD CLASS="arg"
>-&gt; simF</TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="ndoc" COLSPAN="2"
><P
>Generate a function which, given a system definition and some simulation
   stimuli:
</P
><OL
><LI
> Writes a VHDL model of the system 
</LI
><LI
> Simulates the VHDL model with Modelsim getting the results back to Haskell
</LI
></OL
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:writeAndModelsimVHDLOps"
><A NAME="v%3AwriteAndModelsimVHDLOps"
></A
></A
><B
>writeAndModelsimVHDLOps</B
> :: <A HREF="ForSyDe-System.html#t%3ASysFunToIOSimFun"
>SysFunToIOSimFun</A
> sysF simF =&gt; <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
> -&gt; <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
> -&gt; <A HREF="ForSyDe-System.html#t%3ASysDef"
>SysDef</A
> sysF -&gt; simF</TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL.html#writeAndModelsimVHDLOps"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
><TT
><A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
></TT
>-alternative of <TT
><A HREF="ForSyDe-Backend-VHDL.html#v%3AwriteAndModelsimVHDL"
>writeAndModelsimVHDL</A
></TT
>, note that
   compileModelSim will implicitly be set to True
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:VHDLOps"
><A NAME="t%3AVHDLOps"
></A
></A
><B
>VHDLOps</B
>  </TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#VHDLOps"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>VHDL Compilation options
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="5" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:VHDLOps"
><A NAME="v%3AVHDLOps"
></A
></A
><B
>VHDLOps</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="body" COLSPAN="2"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:debugVHDL"
><A NAME="v%3AdebugVHDL"
></A
></A
><B
>debugVHDL</B
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLDebugLevel"
>VHDLDebugLevel</A
></TD
><TD CLASS="rdoc"
>Debug mode
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:recursivityVHDL"
><A NAME="v%3ArecursivityVHDL"
></A
></A
><B
>recursivityVHDL</B
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLRecursivity"
>VHDLRecursivity</A
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:execQuartus"
><A NAME="v%3AexecQuartus"
></A
></A
><B
>execQuartus</B
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusOps"
>QuartusOps</A
></TD
><TD CLASS="rdoc"
>Analyze the generated code with Quartus
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:compileModelsim"
><A NAME="v%3AcompileModelsim"
></A
></A
><B
>compileModelsim</B
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Bool.html#t%3ABool"
>Bool</A
></TD
><TD CLASS="rdoc"
>Compile the generated code with Modelsim
</TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:VHDLOps')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:VHDLOps" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Eq.html#t%3AEq"
>Eq</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Text-Show.html#t%3AShow"
>Show</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:QuartusOps"
><A NAME="t%3AQuartusOps"
></A
></A
><B
>QuartusOps</B
>  </TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#QuartusOps"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
><P
>Options passed to Quartus II by the VHDL Backend. Most of them are optional
   and Quartus will use a default value.
</P
><P
>It contains:
</P
><UL
><LI
> What action to perform
</LI
><LI
> Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz
</LI
><LI
> FPGA family and specific device model (both are independently optional).
</LI
><LI
> Pin assignments, in the form (VHDL Pin, FPGA Pin). Note
       that Quartus will automatically split composite VHDL ports 
</LI
></UL
></TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="5" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:QuartusOps"
><A NAME="v%3AQuartusOps"
></A
></A
><B
>QuartusOps</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="body" COLSPAN="2"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:action"
><A NAME="v%3Aaction"
></A
></A
><B
>action</B
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusAction"
>QuartusAction</A
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:fMax"
><A NAME="v%3AfMax"
></A
></A
><B
>fMax</B
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Int.html#t%3AInt"
>Int</A
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:fpgaFamiliyDevice"
><A NAME="v%3AfpgaFamiliyDevice"
></A
></A
><B
>fpgaFamiliyDevice</B
> :: <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> (<A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>, <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Maybe.html#t%3AMaybe"
>Maybe</A
> <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>)</TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:pinAssigs"
><A NAME="v%3ApinAssigs"
></A
></A
><B
>pinAssigs</B
> :: [(<A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>, <A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Char.html#t%3AString"
>String</A
>)]</TD
><TD CLASS="rdoc"
></TD
></TR
></TABLE
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:QuartusOps')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:QuartusOps" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Eq.html#t%3AEq"
>Eq</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusOps"
>QuartusOps</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Text-Show.html#t%3AShow"
>Show</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusOps"
>QuartusOps</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:QuartusAction"
><A NAME="t%3AQuartusAction"
></A
></A
><B
>QuartusAction</B
>  </TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#QuartusAction"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Action to perform by Quartus
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:AnalysisAndElaboration"
><A NAME="v%3AAnalysisAndElaboration"
></A
></A
><B
>AnalysisAndElaboration</B
></TD
><TD CLASS="rdoc"
>Analysis and eleboration flow
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:AnalysisAndSynthesis"
><A NAME="v%3AAnalysisAndSynthesis"
></A
></A
><B
>AnalysisAndSynthesis</B
></TD
><TD CLASS="rdoc"
>Call map executable 
</TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:FullCompilation"
><A NAME="v%3AFullCompilation"
></A
></A
><B
>FullCompilation</B
></TD
><TD CLASS="rdoc"
>Compile flow
</TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:QuartusAction')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:QuartusAction" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Eq.html#t%3AEq"
>Eq</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusAction"
>QuartusAction</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Text-Show.html#t%3AShow"
>Show</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusAction"
>QuartusAction</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:checkSynthesisQuartus"
><A NAME="v%3AcheckSynthesisQuartus"
></A
></A
><B
>checkSynthesisQuartus</B
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AQuartusOps"
>QuartusOps</A
></TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#checkSynthesisQuartus"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Options to check if the model is synthesizable, all options except
   the action to take are set to default. 
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:VHDLDebugLevel"
><A NAME="t%3AVHDLDebugLevel"
></A
></A
><B
>VHDLDebugLevel</B
>  </TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#VHDLDebugLevel"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Debug level
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:VHDLNormal"
><A NAME="v%3AVHDLNormal"
></A
></A
><B
>VHDLNormal</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:VHDLVerbose"
><A NAME="v%3AVHDLVerbose"
></A
></A
><B
>VHDLVerbose</B
></TD
><TD CLASS="rdoc"
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:VHDLDebugLevel')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:VHDLDebugLevel" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Eq.html#t%3AEq"
>Eq</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLDebugLevel"
>VHDLDebugLevel</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Ord.html#t%3AOrd"
>Ord</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLDebugLevel"
>VHDLDebugLevel</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Text-Show.html#t%3AShow"
>Show</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLDebugLevel"
>VHDLDebugLevel</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><SPAN CLASS="keyword"
>data</SPAN
>  <A NAME="t:VHDLRecursivity"
><A NAME="t%3AVHDLRecursivity"
></A
></A
><B
>VHDLRecursivity</B
>  </TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#VHDLRecursivity"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="0" CELLPADDING="0"
><TR
><TD CLASS="ndoc"
>Recursivity, should the parent systems of system instances be compiled as 
   well?
</TD
></TR
><TR
><TD CLASS="section4"
>Constructors</TD
></TR
><TR
><TD CLASS="body"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="arg"
><A NAME="v:VHDLRecursive"
><A NAME="v%3AVHDLRecursive"
></A
></A
><B
>VHDLRecursive</B
></TD
><TD CLASS="rdoc"
></TD
></TR
><TR
><TD CLASS="arg"
><A NAME="v:VHDLNonRecursive"
><A NAME="v%3AVHDLNonRecursive"
></A
></A
><B
>VHDLNonRecursive</B
></TD
><TD CLASS="rdoc"
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="section4"
><IMG SRC="minus.gif" CLASS="coll" ONCLICK="toggle(this,'i:VHDLRecursivity')" ALT="show/hide"
> Instances</TD
></TR
><TR
><TD CLASS="body"
><DIV ID="i:VHDLRecursivity" STYLE="display:block;"
><TABLE CLASS="vanilla" CELLSPACING="1" CELLPADDING="0"
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Data-Eq.html#t%3AEq"
>Eq</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLRecursivity"
>VHDLRecursivity</A
></TD
></TR
><TR
><TD CLASS="decl"
><A HREF="/usr/share/doc/ghc/html/libraries/base-4.2.0.2/Text-Show.html#t%3AShow"
>Show</A
> <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLRecursivity"
>VHDLRecursivity</A
></TD
></TR
></TABLE
></DIV
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="topdecl"
><TABLE CLASS="declbar"
><TR
><TD CLASS="declname"
><A NAME="v:defaultVHDLOps"
><A NAME="v%3AdefaultVHDLOps"
></A
></A
><B
>defaultVHDLOps</B
> :: <A HREF="ForSyDe-Backend-VHDL.html#t%3AVHDLOps"
>VHDLOps</A
></TD
><TD CLASS="declbut"
><A HREF="src/ForSyDe-Backend-VHDL-Traverse-VHDLM.html#defaultVHDLOps"
>Source</A
></TD
></TR
></TABLE
></TD
></TR
><TR
><TD CLASS="doc"
>Default traversing options
</TD
></TR
><TR
><TD CLASS="s15"
></TD
></TR
><TR
><TD CLASS="botbar"
>Produced by <A HREF="http://www.haskell.org/haddock/"
>Haddock</A
> version 2.6.1</TD
></TR
></TABLE
></BODY
></HTML
>

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