<?xml version="1.0" encoding="UTF-8"?> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd"> <html> <head> <!-- Generated by HsColour, http://www.cs.york.ac.uk/fp/darcs/hscolour/ --> <title>src/ForSyDe/Backend/VHDL/TestBench.hs</title> <link type='text/css' rel='stylesheet' href='hscolour.css' /> </head> <body> <pre><a name="line-1"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span> <a name="line-2"></a><span class='hs-comment'>-- |</span> <a name="line-3"></a><span class='hs-comment'>-- Module : ForSyDe.Backend.VHDL.TestBench</span> <a name="line-4"></a><span class='hs-comment'>-- Copyright : (c) SAM Group, KTH/ICT/ECS 2008</span> <a name="line-5"></a><span class='hs-comment'>-- License : BSD-style (see the file LICENSE)</span> <a name="line-6"></a><span class='hs-comment'>-- </span> <a name="line-7"></a><span class='hs-comment'>-- Maintainer : forsyde-dev@ict.kth.se</span> <a name="line-8"></a><span class='hs-comment'>-- Stability : experimental</span> <a name="line-9"></a><span class='hs-comment'>-- Portability : portable</span> <a name="line-10"></a><span class='hs-comment'>--</span> <a name="line-11"></a><span class='hs-comment'>-- Functions used to generate a VHDL test bech.</span> <a name="line-12"></a><span class='hs-comment'>--</span> <a name="line-13"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span> <a name="line-14"></a><span class='hs-keyword'>module</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>TestBench</span> <a name="line-15"></a> <span class='hs-layout'>(</span><span class='hs-varid'>writeVHDLTestBench</span><span class='hs-layout'>,</span> <a name="line-16"></a> <span class='hs-varid'>parseTestBenchOut</span><span class='hs-layout'>)</span> <span class='hs-keyword'>where</span> <a name="line-17"></a> <a name="line-18"></a> <a name="line-19"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Constants</span> <a name="line-20"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>AST</span> <a name="line-21"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Translate</span> <a name="line-22"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Traverse</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDLM</span> <a name="line-23"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Generate</span> <a name="line-24"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>FileIO</span> <a name="line-25"></a> <a name="line-26"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Ids</span> <a name="line-27"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>SysDef</span> <a name="line-28"></a> <a name="line-29"></a><span class='hs-keyword'>import</span> <span class='hs-keyword'>qualified</span> <span class='hs-conid'>Language</span><span class='hs-varop'>.</span><span class='hs-conid'>Haskell</span><span class='hs-varop'>.</span><span class='hs-conid'>TH</span> <span class='hs-keyword'>as</span> <span class='hs-conid'>TH</span> <span class='hs-layout'>(</span><span class='hs-conid'>Exp</span><span class='hs-layout'>)</span> <a name="line-30"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>Control</span><span class='hs-varop'>.</span><span class='hs-conid'>Monad</span><span class='hs-varop'>.</span><span class='hs-conid'>State</span> <a name="line-31"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>Data</span><span class='hs-varop'>.</span><span class='hs-conid'>List</span> <span class='hs-layout'>(</span><span class='hs-varid'>transpose</span><span class='hs-layout'>)</span> <a name="line-32"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>Directory</span> <a name="line-33"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>FilePath</span> <a name="line-34"></a> <a name="line-35"></a> <a name="line-36"></a><a name="parseTestBenchOut"></a><span class='hs-comment'>-- | Parse the output of the testbench (a tab separated files)</span> <a name="line-37"></a><span class='hs-comment'>-- into strings denoting the individual output signals</span> <a name="line-38"></a><span class='hs-definition'>parseTestBenchOut</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>String</span> <span class='hs-comment'>-- ^ String containing the complete output file</span> <a name="line-39"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>String</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ output signal values in form </span> <a name="line-40"></a> <span class='hs-comment'>-- of strings</span> <a name="line-41"></a><span class='hs-definition'>parseTestBenchOut</span> <span class='hs-varid'>str</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span> <a name="line-42"></a> <span class='hs-varid'>outN</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>length</span><span class='hs-varop'>.</span><span class='hs-varid'>oIface</span><span class='hs-varop'>.</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span> <a name="line-43"></a> <span class='hs-keyword'>case</span> <span class='hs-varid'>tabSeparatedRows</span> <span class='hs-keyword'>of</span> <a name="line-44"></a> <span class='hs-conid'>[]</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-layout'>(</span><span class='hs-varid'>replicate</span> <span class='hs-varid'>outN</span> <span class='hs-conid'>[]</span><span class='hs-layout'>)</span> <a name="line-45"></a> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-varop'>$</span> <span class='hs-varid'>transpose</span> <span class='hs-varid'>tabSeparatedRows</span> <a name="line-46"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>tabSeparatedRows</span> <span class='hs-keyglyph'>=</span> <span class='hs-layout'>(</span><span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-layout'>(</span><span class='hs-varid'>unintersperse</span> <span class='hs-chr'>'\t'</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span><span class='hs-varop'>.</span><span class='hs-varid'>lines</span><span class='hs-layout'>)</span> <span class='hs-varid'>str</span> <a name="line-47"></a> <span class='hs-varid'>unintersperse</span> <span class='hs-keyword'>_</span> <span class='hs-conid'>[]</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>[]</span> <a name="line-48"></a> <span class='hs-varid'>unintersperse</span> <span class='hs-varid'>e</span> <span class='hs-layout'>(</span><span class='hs-varid'>c</span><span class='hs-conop'>:</span><span class='hs-varid'>cs</span><span class='hs-layout'>)</span> <a name="line-49"></a> <span class='hs-comment'>-- the null check makes unintersperse imposible to define with foldr</span> <a name="line-50"></a> <span class='hs-comment'>-- or unfoldr</span> <a name="line-51"></a> <span class='hs-keyglyph'>|</span> <span class='hs-varid'>c</span> <span class='hs-varop'>==</span> <span class='hs-varid'>e</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>if</span> <span class='hs-varid'>null</span> <span class='hs-varid'>cs</span> <span class='hs-keyword'>then</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>[]</span><span class='hs-layout'>,</span><span class='hs-conid'>[]</span><span class='hs-keyglyph'>]</span> <a name="line-52"></a> <span class='hs-keyword'>else</span> <span class='hs-conid'>[]</span> <span class='hs-conop'>:</span> <span class='hs-varid'>unintersperse</span> <span class='hs-varid'>e</span> <span class='hs-varid'>cs</span> <a name="line-53"></a> <span class='hs-keyglyph'>|</span> <span class='hs-varid'>otherwise</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>let</span> <span class='hs-varid'>rest</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>unintersperse</span> <span class='hs-varid'>e</span> <span class='hs-varid'>cs</span> <span class='hs-keyword'>in</span> <a name="line-54"></a> <span class='hs-keyword'>case</span> <span class='hs-varid'>rest</span> <span class='hs-keyword'>of</span> <a name="line-55"></a> <span class='hs-conid'>[]</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-varid'>c</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <a name="line-56"></a> <span class='hs-layout'>(</span><span class='hs-varid'>a</span><span class='hs-conop'>:</span><span class='hs-keyword'>as</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-layout'>(</span><span class='hs-varid'>c</span><span class='hs-conop'>:</span><span class='hs-varid'>a</span><span class='hs-layout'>)</span><span class='hs-conop'>:</span><span class='hs-keyword'>as</span> <a name="line-57"></a> <a name="line-58"></a><a name="writeVHDLTestBench"></a><span class='hs-comment'>-- | write a test bench, using a clock cycle of 10 ns</span> <a name="line-59"></a><span class='hs-comment'>-- (Note: the initial and final CWD will be / )</span> <a name="line-60"></a><span class='hs-definition'>writeVHDLTestBench</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>Maybe</span> <span class='hs-conid'>Int</span> <span class='hs-comment'>-- ^ Number of cycles to simulate</span> <a name="line-61"></a> <span class='hs-comment'>-- if 'Nothing' the number will be determined</span> <a name="line-62"></a> <span class='hs-comment'>-- by the length of the input stimulti.</span> <a name="line-63"></a> <span class='hs-comment'>-- Useful when the system to simulate doesn't</span> <a name="line-64"></a> <span class='hs-comment'>-- have inputs or the inputs provided are </span> <a name="line-65"></a> <span class='hs-comment'>-- infinite</span> <a name="line-66"></a> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>TH</span><span class='hs-varop'>.</span><span class='hs-conid'>Exp</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ Input stimuli (one list per signal)</span> <a name="line-67"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-conid'>Int</span> <span class='hs-comment'>-- ^ Number of cycles simulated</span> <a name="line-68"></a><span class='hs-definition'>writeVHDLTestBench</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>stimuli</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span> <a name="line-69"></a> <span class='hs-varid'>sys</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span> <a name="line-70"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>sysId</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>sid</span> <span class='hs-varid'>sys</span> <a name="line-71"></a> <span class='hs-varid'>cxt</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genVHDLTestBenchContext</span> <span class='hs-varid'>sysId</span> <a name="line-72"></a> <span class='hs-varid'>ent</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genVHDLTestBenchEntity</span> <span class='hs-varid'>sysId</span> <a name="line-73"></a> <span class='hs-layout'>(</span><span class='hs-varid'>arch</span><span class='hs-layout'>,</span> <span class='hs-varid'>cycles</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>genVHDLTestBenchArch</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>stimuli</span> <a name="line-74"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>design</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>DesignFile</span> <span class='hs-varid'>cxt</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>LUEntity</span> <span class='hs-varid'>ent</span><span class='hs-layout'>,</span> <span class='hs-conid'>LUArch</span> <span class='hs-varid'>arch</span><span class='hs-keyglyph'>]</span> <a name="line-75"></a> <span class='hs-varid'>tbdir</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>sysId</span> <span class='hs-varop'></></span> <span class='hs-str'>"vhdl"</span> <span class='hs-varop'></></span> <span class='hs-str'>"test"</span> <a name="line-76"></a> <span class='hs-varid'>tbpath</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>tbdir</span> <span class='hs-varop'></></span> <span class='hs-layout'>(</span><span class='hs-varid'>sysId</span> <span class='hs-varop'>++</span> <span class='hs-str'>"_tb.vhd"</span><span class='hs-layout'>)</span> <a name="line-77"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>createDirectoryIfMissing</span> <span class='hs-conid'>True</span> <span class='hs-varid'>tbdir</span> <a name="line-78"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>writeDesignFile</span> <span class='hs-varid'>design</span> <span class='hs-varid'>tbpath</span> <a name="line-79"></a> <span class='hs-varid'>return</span> <span class='hs-varid'>cycles</span> <a name="line-80"></a> <a name="line-81"></a><a name="genVHDLTestBenchContext"></a><span class='hs-comment'>-- | Generate the Context Clause</span> <a name="line-82"></a><span class='hs-definition'>genVHDLTestBenchContext</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>SysId</span> <span class='hs-comment'>-- ^ Main system Id</span> <a name="line-83"></a> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>ContextItem</span><span class='hs-keyglyph'>]</span> <a name="line-84"></a><span class='hs-definition'>genVHDLTestBenchContext</span> <span class='hs-varid'>id</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>commonContextClause</span> <span class='hs-varop'>++</span> <a name="line-85"></a> <span class='hs-keyglyph'>[</span><span class='hs-conid'>Library</span> <span class='hs-varid'>libId</span><span class='hs-layout'>,</span> <a name="line-86"></a> <span class='hs-conid'>Use</span> <span class='hs-varop'>$</span> <span class='hs-conid'>NSelected</span> <span class='hs-layout'>(</span><span class='hs-conid'>NSimple</span> <span class='hs-varid'>libId</span> <span class='hs-conop'>:.:</span> <span class='hs-conid'>SSimple</span> <span class='hs-varid'>typesId</span><span class='hs-layout'>)</span> <span class='hs-conop'>:.:</span> <span class='hs-conid'>All</span><span class='hs-layout'>,</span> <a name="line-87"></a> <span class='hs-conid'>Use</span> <span class='hs-varop'>$</span> <span class='hs-conid'>NSelected</span> <span class='hs-layout'>(</span><span class='hs-conid'>NSimple</span> <span class='hs-varid'>stdId</span> <span class='hs-conop'>:.:</span> <span class='hs-conid'>SSimple</span> <span class='hs-varid'>textioId</span><span class='hs-layout'>)</span> <span class='hs-conop'>:.:</span> <span class='hs-conid'>All</span><span class='hs-keyglyph'>]</span> <a name="line-88"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>libId</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-layout'>(</span><span class='hs-varid'>id</span> <span class='hs-varop'>++</span> <span class='hs-str'>"_lib"</span><span class='hs-layout'>)</span> <a name="line-89"></a> <a name="line-90"></a><a name="genVHDLTestBenchEntity"></a><span class='hs-comment'>-- | Generates an empty entity fot the testbench</span> <a name="line-91"></a><span class='hs-definition'>genVHDLTestBenchEntity</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>SysId</span> <span class='hs-comment'>-- ^ Main system Id </span> <a name="line-92"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>EntityDec</span> <a name="line-93"></a><span class='hs-definition'>genVHDLTestBenchEntity</span> <span class='hs-varid'>id</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>EntityDec</span> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-layout'>(</span><span class='hs-varid'>id</span> <span class='hs-varop'>++</span> <span class='hs-str'>"_tb"</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <span class='hs-conid'>[]</span> <a name="line-94"></a> <a name="line-95"></a><span class='hs-comment'>--------------------------</span> <a name="line-96"></a><span class='hs-comment'>-- Test Bench Architecture</span> <a name="line-97"></a><span class='hs-comment'>--------------------------</span> <a name="line-98"></a> <a name="line-99"></a> <a name="line-100"></a><a name="genVHDLTestBenchArch"></a><span class='hs-comment'>-- | generate the architecture</span> <a name="line-101"></a><span class='hs-definition'>genVHDLTestBenchArch</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>Maybe</span> <span class='hs-conid'>Int</span> <span class='hs-comment'>-- ^ Maximum number of cycles</span> <a name="line-102"></a> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>TH</span><span class='hs-varop'>.</span><span class='hs-conid'>Exp</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ Input stimuli </span> <a name="line-103"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-layout'>(</span><span class='hs-conid'>ArchBody</span><span class='hs-layout'>,</span> <span class='hs-conid'>Int</span><span class='hs-layout'>)</span> <span class='hs-comment'>-- ^ Number of cycles simulated</span> <a name="line-104"></a><span class='hs-definition'>genVHDLTestBenchArch</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>stimuli</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span> <a name="line-105"></a> <span class='hs-varid'>sys</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span> <a name="line-106"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>sysId</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>sid</span> <span class='hs-varid'>sys</span> <a name="line-107"></a> <span class='hs-varid'>iface</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>iIface</span> <span class='hs-varid'>sys</span> <a name="line-108"></a> <span class='hs-varid'>oface</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>oIface</span> <span class='hs-varid'>sys</span> <a name="line-109"></a> <span class='hs-varid'>l</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>logic</span> <span class='hs-varid'>sys</span> <a name="line-110"></a> <span class='hs-varid'>iIds</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>map</span> <span class='hs-varid'>fst</span> <span class='hs-varid'>iface</span> <a name="line-111"></a> <span class='hs-varid'>iVHDLIds</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>map</span> <span class='hs-varid'>unsafeVHDLExtId</span> <span class='hs-varid'>iIds</span> <a name="line-112"></a> <span class='hs-varid'>oIds</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>map</span> <span class='hs-varid'>fst</span> <span class='hs-varid'>oface</span> <a name="line-113"></a> <span class='hs-comment'>-- Get the signal declarations for the input signals</span> <a name="line-114"></a> <span class='hs-varid'>iDecs</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>mapM</span> <a name="line-115"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-layout'>(</span><span class='hs-varid'>pId</span><span class='hs-layout'>,</span> <span class='hs-varid'>t</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>transVHDLName2SigDec</span> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLExtId</span> <span class='hs-varid'>pId</span><span class='hs-layout'>)</span> <span class='hs-varid'>t</span> <span class='hs-conid'>Nothing</span><span class='hs-layout'>)</span> <span class='hs-varid'>iface</span> <a name="line-116"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>finalIDecs</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>iDecs</span> <span class='hs-varop'>++</span> <a name="line-117"></a> <span class='hs-keyglyph'>[</span><span class='hs-conid'>SigDec</span> <span class='hs-varid'>clockId</span> <span class='hs-varid'>std_logicTM</span> <span class='hs-layout'>(</span><span class='hs-conid'>Just</span> <span class='hs-varop'>$</span> <span class='hs-conid'>PrimLit</span> <span class='hs-str'>"'0'"</span><span class='hs-layout'>)</span><span class='hs-layout'>,</span> <a name="line-118"></a> <span class='hs-conid'>SigDec</span> <span class='hs-varid'>resetId</span> <span class='hs-varid'>std_logicTM</span> <span class='hs-layout'>(</span><span class='hs-conid'>Just</span> <span class='hs-varop'>$</span> <span class='hs-conid'>PrimLit</span> <span class='hs-str'>"'0'"</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span> <a name="line-119"></a> <span class='hs-comment'>-- Get the component instantiation and the signal declarations for the output</span> <a name="line-120"></a> <span class='hs-comment'>-- signals</span> <a name="line-121"></a> <span class='hs-layout'>(</span><span class='hs-varid'>mIns</span><span class='hs-layout'>,</span> <span class='hs-varid'>outDecs</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <a name="line-122"></a> <span class='hs-varid'>transSysIns2CompIns</span> <span class='hs-varid'>l</span> <a name="line-123"></a> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-str'>"totest"</span><span class='hs-layout'>)</span> <a name="line-124"></a> <span class='hs-varid'>iVHDLIds</span> <a name="line-125"></a> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-layout'>(</span><span class='hs-varid'>id</span><span class='hs-layout'>,</span> <span class='hs-varid'>t</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLExtId</span> <span class='hs-varid'>id</span><span class='hs-layout'>,</span><span class='hs-varid'>t</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <span class='hs-varid'>oface</span><span class='hs-layout'>)</span> <a name="line-126"></a> <span class='hs-varid'>sysId</span> <a name="line-127"></a> <span class='hs-varid'>iIds</span> <a name="line-128"></a> <span class='hs-varid'>oIds</span> <a name="line-129"></a> <span class='hs-comment'>-- Generate the signal assignments</span> <a name="line-130"></a> <span class='hs-layout'>(</span><span class='hs-varid'>stimuliAssigns</span><span class='hs-layout'>,</span> <span class='hs-varid'>cycles</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>genStimuliAssigns</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>stimuli</span> <span class='hs-varid'>iVHDLIds</span> <a name="line-131"></a> <span class='hs-comment'>-- Add an assignment to turn off the reset signal after 3 ns</span> <a name="line-132"></a> <span class='hs-comment'>-- (everything lower than 5 ns should work)</span> <a name="line-133"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>finalAssigns</span> <span class='hs-keyglyph'>=</span> <a name="line-134"></a> <span class='hs-layout'>(</span><span class='hs-conid'>NSimple</span> <span class='hs-varid'>resetId</span> <span class='hs-conop'>:<==:</span> <a name="line-135"></a> <span class='hs-conid'>ConWforms</span> <span class='hs-conid'>[]</span> <a name="line-136"></a> <span class='hs-layout'>(</span><span class='hs-conid'>Wform</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>WformElem</span> <span class='hs-layout'>(</span><span class='hs-conid'>PrimLit</span> <span class='hs-str'>"'1'"</span><span class='hs-layout'>)</span> <span class='hs-layout'>(</span><span class='hs-conid'>Just</span> <span class='hs-varop'>$</span> <span class='hs-conid'>PrimLit</span> <span class='hs-str'>"3 ns"</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>)</span> <a name="line-137"></a> <span class='hs-conid'>Nothing</span><span class='hs-layout'>)</span> <span class='hs-conop'>:</span> <span class='hs-varid'>stimuliAssigns</span> <a name="line-138"></a> <span class='hs-comment'>-- Get the two processes (clock and output)</span> <a name="line-139"></a> <span class='hs-varid'>clkProc</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genClkProc</span> <a name="line-140"></a> <span class='hs-varid'>outputProc</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genOutputProc</span> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-varid'>unsafeVHDLExtId</span> <span class='hs-varid'>oIds</span><span class='hs-layout'>)</span> <a name="line-141"></a> <span class='hs-comment'>-- return the architecture</span> <a name="line-142"></a> <span class='hs-varid'>return</span> <span class='hs-varop'>$</span> <span class='hs-layout'>(</span><span class='hs-conid'>ArchBody</span> <a name="line-143"></a> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-str'>"test"</span><span class='hs-layout'>)</span> <a name="line-144"></a> <span class='hs-layout'>(</span><span class='hs-conid'>NSimple</span> <span class='hs-varop'>$</span> <span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-layout'>(</span><span class='hs-varid'>sysId</span> <span class='hs-varop'>++</span> <span class='hs-str'>"_tb"</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <a name="line-145"></a> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-conid'>BDISD</span> <span class='hs-layout'>(</span><span class='hs-varid'>finalIDecs</span> <span class='hs-varop'>++</span> <span class='hs-varid'>outDecs</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <a name="line-146"></a> <span class='hs-layout'>(</span> <span class='hs-varid'>maybe</span> <span class='hs-conid'>[]</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-varid'>s</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>CSISm</span> <span class='hs-varid'>s</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>)</span> <span class='hs-varid'>mIns</span> <span class='hs-varop'>++</span> <a name="line-147"></a> <span class='hs-layout'>(</span> <span class='hs-layout'>(</span><span class='hs-conid'>CSPSm</span> <span class='hs-varid'>clkProc</span><span class='hs-layout'>)</span> <span class='hs-conop'>:</span> <span class='hs-layout'>(</span><span class='hs-conid'>CSPSm</span> <span class='hs-varid'>outputProc</span><span class='hs-layout'>)</span> <span class='hs-conop'>:</span> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-conid'>CSSASm</span> <span class='hs-varid'>finalAssigns</span><span class='hs-layout'>)</span> <span class='hs-layout'>)</span> <span class='hs-layout'>)</span><span class='hs-layout'>,</span> <a name="line-148"></a> <span class='hs-varid'>cycles</span><span class='hs-layout'>)</span> <a name="line-149"></a> <a name="line-150"></a><a name="genStimuliAssigns"></a><span class='hs-comment'>-- | generate the assignments for the input stimuli</span> <a name="line-151"></a><span class='hs-definition'>genStimuliAssigns</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>Maybe</span> <span class='hs-conid'>Int</span> <span class='hs-comment'>-- ^ Maximum number of cycles</span> <a name="line-152"></a> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>TH</span><span class='hs-varop'>.</span><span class='hs-conid'>Exp</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ Input stimuli </span> <a name="line-153"></a> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>VHDLId</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ Input signal ids</span> <a name="line-154"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>ConSigAssignSm</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>,</span> <span class='hs-conid'>Int</span><span class='hs-layout'>)</span> <span class='hs-comment'>-- ^ (Assignments,</span> <a name="line-155"></a> <span class='hs-comment'>-- number of cycles </span> <a name="line-156"></a> <span class='hs-comment'>-- simulated)</span> <a name="line-157"></a><span class='hs-comment'>-- if the number of input signas is zero</span> <a name="line-158"></a><span class='hs-definition'>genStimuliAssigns</span> <span class='hs-varid'>mCycles</span> <span class='hs-conid'>[]</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>return</span> <span class='hs-layout'>(</span><span class='hs-conid'>[]</span><span class='hs-layout'>,</span> <span class='hs-varid'>maybe</span> <span class='hs-num'>0</span> <span class='hs-varid'>id</span> <span class='hs-varid'>mCycles</span><span class='hs-layout'>)</span> <a name="line-159"></a> <a name="line-160"></a><span class='hs-comment'>-- if the nu,ber of input signals is /= zero</span> <a name="line-161"></a><span class='hs-definition'>genStimuliAssigns</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>stimuli</span> <span class='hs-varid'>signals</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span> <a name="line-162"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>genWformElem</span> <span class='hs-varid'>time</span> <span class='hs-varid'>thExp</span> <span class='hs-keyglyph'>=</span> <a name="line-163"></a> <span class='hs-keyword'>do</span> <span class='hs-varid'>vExp</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transExp2VHDL</span> <span class='hs-varid'>thExp</span> <a name="line-164"></a> <span class='hs-varid'>return</span> <span class='hs-layout'>(</span><span class='hs-conid'>WformElem</span> <span class='hs-varid'>vExp</span> <span class='hs-layout'>(</span><span class='hs-conid'>Just</span> <span class='hs-varop'>$</span> <span class='hs-conid'>PrimLit</span> <span class='hs-layout'>(</span><span class='hs-varid'>show</span> <span class='hs-varid'>time</span> <span class='hs-varop'>++</span> <span class='hs-str'>" ns"</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <a name="line-165"></a> <span class='hs-varid'>wformElems</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>mapM</span> <span class='hs-layout'>(</span><span class='hs-varid'>zipWithM</span> <span class='hs-varid'>genWformElem</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-num'>0</span><span class='hs-layout'>,</span><span class='hs-num'>10</span><span class='hs-keyglyph'>..</span><span class='hs-keyglyph'>]</span> <span class='hs-keyglyph'>::</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>Int</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <span class='hs-varid'>stimuli</span> <a name="line-166"></a> <span class='hs-keyword'>let</span> <span class='hs-layout'>(</span><span class='hs-varid'>normWformElems</span><span class='hs-layout'>,</span> <span class='hs-varid'>cycles</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>normalize</span> <span class='hs-varid'>maxCycles</span> <span class='hs-varid'>wformElems</span> <a name="line-167"></a> <span class='hs-keyword'>if</span> <span class='hs-varid'>cycles</span> <span class='hs-varop'>==</span> <span class='hs-num'>0</span> <a name="line-168"></a> <span class='hs-keyword'>then</span> <span class='hs-varid'>return</span> <span class='hs-layout'>(</span><span class='hs-conid'>[]</span><span class='hs-layout'>,</span><span class='hs-num'>0</span><span class='hs-layout'>)</span> <a name="line-169"></a> <span class='hs-keyword'>else</span> <span class='hs-varid'>return</span> <a name="line-170"></a> <span class='hs-layout'>(</span><span class='hs-varid'>zipWith</span> <a name="line-171"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-varid'>s</span> <span class='hs-varid'>elems</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>NSimple</span> <span class='hs-varid'>s</span> <span class='hs-conop'>:<==:</span> <span class='hs-conid'>ConWforms</span> <span class='hs-conid'>[]</span> <span class='hs-layout'>(</span><span class='hs-conid'>Wform</span> <span class='hs-varid'>elems</span><span class='hs-layout'>)</span> <span class='hs-conid'>Nothing</span><span class='hs-layout'>)</span> <a name="line-172"></a> <span class='hs-varid'>signals</span> <a name="line-173"></a> <span class='hs-varid'>normWformElems</span><span class='hs-layout'>,</span> <a name="line-174"></a> <span class='hs-varid'>cycles</span><span class='hs-layout'>)</span> <a name="line-175"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>maxCycles</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>maybe</span> <span class='hs-layout'>(</span><span class='hs-comment'>-</span><span class='hs-num'>1</span><span class='hs-layout'>)</span> <span class='hs-varid'>id</span> <span class='hs-varid'>mCycles</span> <a name="line-176"></a> <span class='hs-comment'>-- FIXME: this is not efficient at all</span> <a name="line-177"></a> <span class='hs-comment'>-- Normalize a matrix. Make sure that all the rows in a matrix have the</span> <a name="line-178"></a> <span class='hs-comment'>-- same length, setting a maximum row length (0 establishes no limit)</span> <a name="line-179"></a> <span class='hs-varid'>normalize</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>Int</span> <span class='hs-comment'>-- ^ maximum row-length to process </span> <a name="line-180"></a> <span class='hs-keyglyph'>-></span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-varid'>a</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ input matrix</span> <a name="line-181"></a> <span class='hs-keyglyph'>-></span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-varid'>a</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>,</span> <span class='hs-conid'>Int</span><span class='hs-layout'>)</span> <span class='hs-comment'>-- ^ (output matrix, maximum row length)</span> <a name="line-182"></a> <span class='hs-varid'>normalize</span> <span class='hs-varid'>max</span> <span class='hs-varid'>xss</span> <a name="line-183"></a> <span class='hs-keyglyph'>|</span> <span class='hs-varid'>any</span> <span class='hs-varid'>null</span> <span class='hs-varid'>xss</span> <span class='hs-varop'>||</span> <span class='hs-varid'>max</span> <span class='hs-varop'>==</span> <span class='hs-num'>0</span> <span class='hs-keyglyph'>=</span> <span class='hs-layout'>(</span><span class='hs-varid'>replicate</span> <span class='hs-varid'>l</span> <span class='hs-conid'>[]</span><span class='hs-layout'>,</span> <span class='hs-num'>0</span><span class='hs-layout'>)</span> <a name="line-184"></a> <span class='hs-keyglyph'>|</span> <span class='hs-varid'>otherwise</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>let</span> <span class='hs-layout'>(</span><span class='hs-varid'>transres</span><span class='hs-layout'>,</span> <span class='hs-varid'>acum</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>normalize'</span> <span class='hs-varid'>max</span> <span class='hs-layout'>(</span><span class='hs-varid'>transpose</span> <span class='hs-varid'>xss</span><span class='hs-layout'>)</span> <a name="line-185"></a> <span class='hs-keyword'>in</span> <span class='hs-layout'>(</span><span class='hs-varid'>transpose</span> <span class='hs-varid'>transres</span><span class='hs-layout'>,</span> <span class='hs-varid'>acum</span><span class='hs-layout'>)</span> <a name="line-186"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>l</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>length</span> <span class='hs-varid'>xss</span> <a name="line-187"></a> <span class='hs-varid'>normalize'</span> <span class='hs-varid'>max</span> <span class='hs-layout'>(</span><span class='hs-varid'>xs</span><span class='hs-conop'>:</span><span class='hs-varid'>xss</span><span class='hs-layout'>)</span> <a name="line-188"></a> <span class='hs-keyglyph'>|</span> <span class='hs-varid'>length</span> <span class='hs-varid'>xs</span> <span class='hs-varop'>==</span> <span class='hs-varid'>l</span> <span class='hs-varop'>&&</span> <span class='hs-varid'>max</span> <span class='hs-varop'>/=</span> <span class='hs-num'>0</span> <span class='hs-keyglyph'>=</span> <a name="line-189"></a> <span class='hs-keyword'>let</span> <span class='hs-layout'>(</span><span class='hs-varid'>nextlist</span><span class='hs-layout'>,</span> <span class='hs-varid'>nextacum</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>normalize'</span> <span class='hs-layout'>(</span><span class='hs-varid'>max</span><span class='hs-comment'>-</span><span class='hs-num'>1</span><span class='hs-layout'>)</span> <span class='hs-varid'>xss</span> <a name="line-190"></a> <span class='hs-keyword'>in</span> <span class='hs-layout'>(</span><span class='hs-varid'>xs</span> <span class='hs-conop'>:</span> <span class='hs-varid'>nextlist</span><span class='hs-layout'>,</span> <span class='hs-varid'>nextacum</span><span class='hs-varop'>+</span><span class='hs-num'>1</span><span class='hs-layout'>)</span> <a name="line-191"></a> <span class='hs-varid'>normalize'</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>=</span> <span class='hs-layout'>(</span><span class='hs-conid'>[]</span><span class='hs-layout'>,</span> <span class='hs-num'>0</span><span class='hs-layout'>)</span> <a name="line-192"></a> <a name="line-193"></a><a name="genClkProc"></a><span class='hs-comment'>-- | generates a clock process with a period of 10ns</span> <a name="line-194"></a><span class='hs-definition'>genClkProc</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>ProcSm</span> <a name="line-195"></a><span class='hs-definition'>genClkProc</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>ProcSm</span> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-str'>"clkproc"</span><span class='hs-layout'>)</span> <span class='hs-conid'>[]</span> <span class='hs-varid'>sms</span> <a name="line-196"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>sms</span> <span class='hs-keyglyph'>=</span> <span class='hs-comment'>-- wait for 5 ns -- (half a cycle)</span> <a name="line-197"></a> <span class='hs-keyglyph'>[</span><span class='hs-conid'>WaitFor</span> <span class='hs-varop'>$</span> <span class='hs-conid'>PrimLit</span> <span class='hs-str'>"5 ns"</span><span class='hs-layout'>,</span> <a name="line-198"></a> <span class='hs-comment'>-- clk <= not clk;</span> <a name="line-199"></a> <span class='hs-conid'>NSimple</span> <span class='hs-varid'>clockId</span> <span class='hs-varop'>`SigAssign`</span> <a name="line-200"></a> <span class='hs-conid'>Wform</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>WformElem</span> <span class='hs-layout'>(</span><span class='hs-conid'>Not</span> <span class='hs-layout'>(</span><span class='hs-conid'>PrimName</span> <span class='hs-varop'>$</span> <span class='hs-conid'>NSimple</span> <span class='hs-varid'>clockId</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <span class='hs-conid'>Nothing</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <a name="line-201"></a> <a name="line-202"></a><a name="genOutputProc"></a><span class='hs-comment'>-- | generate the output process</span> <a name="line-203"></a><span class='hs-definition'>genOutputProc</span> <span class='hs-keyglyph'>::</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>VHDLId</span><span class='hs-keyglyph'>]</span> <span class='hs-comment'>-- ^ output signals</span> <a name="line-204"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>ProcSm</span> <a name="line-205"></a><span class='hs-definition'>genOutputProc</span> <span class='hs-varid'>outs</span> <span class='hs-keyglyph'>=</span> <a name="line-206"></a> <span class='hs-conid'>ProcSm</span> <span class='hs-layout'>(</span><span class='hs-varid'>unsafeVHDLBasicId</span> <span class='hs-str'>"writeoutput"</span><span class='hs-layout'>)</span> <a name="line-207"></a> <span class='hs-keyglyph'>[</span><span class='hs-varid'>clockId</span><span class='hs-keyglyph'>]</span> <a name="line-208"></a> <span class='hs-keyglyph'>[</span><span class='hs-conid'>IfSm</span> <span class='hs-varid'>clkPred</span> <span class='hs-layout'>(</span><span class='hs-varid'>writeOuts</span> <span class='hs-varid'>outs</span><span class='hs-layout'>)</span> <span class='hs-conid'>[]</span> <span class='hs-conid'>Nothing</span><span class='hs-keyglyph'>]</span> <a name="line-209"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>clkPred</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>PrimName</span> <span class='hs-layout'>(</span><span class='hs-conid'>NAttribute</span> <span class='hs-varop'>$</span> <span class='hs-conid'>AttribName</span> <span class='hs-layout'>(</span><span class='hs-conid'>NSimple</span> <span class='hs-varid'>clockId</span><span class='hs-layout'>)</span> <a name="line-210"></a> <span class='hs-varid'>eventId</span> <a name="line-211"></a> <span class='hs-conid'>Nothing</span> <span class='hs-layout'>)</span> <span class='hs-varop'>`And`</span> <a name="line-212"></a> <span class='hs-layout'>(</span><span class='hs-conid'>PrimName</span> <span class='hs-layout'>(</span><span class='hs-conid'>NSimple</span> <span class='hs-varid'>clockId</span><span class='hs-layout'>)</span> <span class='hs-conop'>:=:</span> <span class='hs-conid'>PrimLit</span> <span class='hs-str'>"'1'"</span><span class='hs-layout'>)</span> <a name="line-213"></a> <span class='hs-varid'>writeOuts</span> <span class='hs-conid'>[]</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>[]</span> <a name="line-214"></a> <span class='hs-varid'>writeOuts</span> <span class='hs-keyglyph'>[</span><span class='hs-varid'>i</span><span class='hs-keyglyph'>]</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyglyph'>[</span><span class='hs-varid'>writeOut</span> <span class='hs-varid'>i</span> <span class='hs-layout'>(</span><span class='hs-conid'>PrimLit</span> <span class='hs-str'>"LF"</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span> <a name="line-215"></a> <span class='hs-varid'>writeOuts</span> <span class='hs-layout'>(</span><span class='hs-varid'>i</span><span class='hs-conop'>:</span><span class='hs-varid'>is</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>writeOut</span> <span class='hs-varid'>i</span> <span class='hs-layout'>(</span><span class='hs-conid'>PrimLit</span> <span class='hs-str'>"HT"</span><span class='hs-layout'>)</span> <span class='hs-conop'>:</span> <span class='hs-varid'>writeOuts</span> <span class='hs-varid'>is</span> <a name="line-216"></a> <span class='hs-varid'>writeOut</span> <span class='hs-varid'>outSig</span> <span class='hs-varid'>suffix</span> <span class='hs-keyglyph'>=</span> <a name="line-217"></a> <span class='hs-varid'>genExprProcCall2</span> <span class='hs-varid'>writeId</span> <a name="line-218"></a> <span class='hs-layout'>(</span><span class='hs-conid'>PrimName</span> <span class='hs-varop'>$</span> <span class='hs-conid'>NSimple</span> <span class='hs-varid'>outputId</span><span class='hs-layout'>)</span> <a name="line-219"></a> <span class='hs-layout'>(</span><span class='hs-varid'>genExprFCall1</span> <span class='hs-varid'>showId</span> <span class='hs-layout'>(</span><span class='hs-conid'>PrimName</span> <span class='hs-varop'>$</span> <span class='hs-conid'>NSimple</span> <span class='hs-varid'>outSig</span><span class='hs-layout'>)</span> <span class='hs-conop'>:&:</span> <a name="line-220"></a> <span class='hs-varid'>suffix</span><span class='hs-layout'>)</span> </pre></body> </html>
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