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<pre><a name="line-1"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span>
<a name="line-2"></a><span class='hs-comment'>-- |</span>
<a name="line-3"></a><span class='hs-comment'>-- Module : ForSyDe.Backend.VHDL.Traverse</span>
<a name="line-4"></a><span class='hs-comment'>-- Copyright : (c) SAM Group, KTH/ICT/ECS 2007-2008</span>
<a name="line-5"></a><span class='hs-comment'>-- License : BSD-style (see the file LICENSE)</span>
<a name="line-6"></a><span class='hs-comment'>-- </span>
<a name="line-7"></a><span class='hs-comment'>-- Maintainer : forsyde-dev@ict.kth.se</span>
<a name="line-8"></a><span class='hs-comment'>-- Stability : experimental</span>
<a name="line-9"></a><span class='hs-comment'>-- Portability : portable</span>
<a name="line-10"></a><span class='hs-comment'>--</span>
<a name="line-11"></a><span class='hs-comment'>-- This module provides specialized Netlist traversing functions aimed at</span>
<a name="line-12"></a><span class='hs-comment'>-- VHDL compilation.</span>
<a name="line-13"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span>
<a name="line-14"></a><span class='hs-keyword'>module</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Traverse</span>
<a name="line-15"></a> <span class='hs-layout'>(</span><span class='hs-varid'>writeVHDLM</span><span class='hs-layout'>,</span>
<a name="line-16"></a> <span class='hs-keyword'>module</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Traverse</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDLM</span><span class='hs-layout'>)</span> <span class='hs-keyword'>where</span>
<a name="line-17"></a>
<a name="line-18"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Traverse</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDLM</span>
<a name="line-19"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Translate</span>
<a name="line-20"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Generate</span>
<a name="line-21"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>FileIO</span>
<a name="line-22"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>AST</span>
<a name="line-23"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Quartus</span> <span class='hs-layout'>(</span><span class='hs-varid'>callQuartus</span><span class='hs-layout'>)</span>
<a name="line-24"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Modelsim</span>
<a name="line-25"></a>
<a name="line-26"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>ForSyDeErr</span>
<a name="line-27"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>SysDef</span>
<a name="line-28"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Process</span><span class='hs-varop'>.</span><span class='hs-conid'>ProcVal</span>
<a name="line-29"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Process</span><span class='hs-varop'>.</span><span class='hs-conid'>ProcFun</span>
<a name="line-30"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Netlist</span><span class='hs-varop'>.</span><span class='hs-conid'>Traverse</span>
<a name="line-31"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Netlist</span>
<a name="line-32"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>OSharing</span>
<a name="line-33"></a>
<a name="line-34"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>Control</span><span class='hs-varop'>.</span><span class='hs-conid'>Monad</span><span class='hs-varop'>.</span><span class='hs-conid'>State</span>
<a name="line-35"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>Directory</span>
<a name="line-36"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>FilePath</span>
<a name="line-37"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>Data</span><span class='hs-varop'>.</span><span class='hs-conid'>Maybe</span> <span class='hs-layout'>(</span><span class='hs-varid'>fromJust</span><span class='hs-layout'>,</span> <span class='hs-varid'>isJust</span><span class='hs-layout'>)</span>
<a name="line-38"></a>
<a name="line-39"></a><a name="writeVHDLM"></a><span class='hs-comment'>-- | Internal VHDL-Monad version of 'ForSyDe.Backend.writeVHDL'</span>
<a name="line-40"></a><span class='hs-comment'>-- (Note: the initial and final CWD will be / )</span>
<a name="line-41"></a><span class='hs-definition'>writeVHDLM</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>VHDLM</span> <span class='hs-conid'>()</span>
<a name="line-42"></a><span class='hs-definition'>writeVHDLM</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-43"></a> <span class='hs-comment'>-- create and change to systemName/vhdl/work</span>
<a name="line-44"></a> <span class='hs-varid'>rootDir</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>sid</span><span class='hs-varop'>.</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span>
<a name="line-45"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>workDir</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>rootDir</span> <span class='hs-varop'></></span> <span class='hs-str'>"vhdl"</span> <span class='hs-varop'></></span> <span class='hs-str'>"work"</span>
<a name="line-46"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>createDirectoryIfMissing</span> <span class='hs-conid'>True</span> <span class='hs-varid'>workDir</span>
<a name="line-47"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>setCurrentDirectory</span> <span class='hs-varid'>workDir</span>
<a name="line-48"></a> <span class='hs-comment'>-- if we are in recursive mode, also write the local results</span>
<a name="line-49"></a> <span class='hs-comment'>-- for the rest of the subsystems</span>
<a name="line-50"></a> <span class='hs-varid'>rec</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>isRecursiveSet</span>
<a name="line-51"></a> <span class='hs-varid'>when</span> <span class='hs-varid'>rec</span> <span class='hs-varop'>$</span> <span class='hs-keyword'>do</span> <span class='hs-varid'>subs</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>subSys</span><span class='hs-varop'>.</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span>
<a name="line-52"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>writeSub</span> <span class='hs-varid'>s</span> <span class='hs-keyglyph'>=</span>
<a name="line-53"></a> <span class='hs-varid'>withLocalST</span> <span class='hs-layout'>(</span><span class='hs-varid'>initLocalST</span> <span class='hs-layout'>(</span><span class='hs-layout'>(</span><span class='hs-varid'>readURef</span><span class='hs-varop'>.</span><span class='hs-varid'>unPrimSysDef</span><span class='hs-layout'>)</span> <span class='hs-varid'>s</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span>
<a name="line-54"></a> <span class='hs-varid'>writeLocalVHDLM</span>
<a name="line-55"></a> <span class='hs-varid'>mapM_</span> <span class='hs-varid'>writeSub</span> <span class='hs-varid'>subs</span>
<a name="line-56"></a> <span class='hs-comment'>-- write the local results for the first-level entity</span>
<a name="line-57"></a> <span class='hs-varid'>writeLocalVHDLM</span>
<a name="line-58"></a> <span class='hs-comment'>-- create and change to systemName/vhdl/systemName_lib</span>
<a name="line-59"></a> <span class='hs-comment'>-- (remember we are in workDir)</span>
<a name="line-60"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>libDir</span> <span class='hs-keyglyph'>=</span> <span class='hs-str'>".."</span> <span class='hs-varop'></></span> <span class='hs-varid'>rootDir</span> <span class='hs-varop'>++</span> <span class='hs-str'>"_lib"</span>
<a name="line-61"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>createDirectoryIfMissing</span> <span class='hs-conid'>True</span> <span class='hs-varid'>libDir</span>
<a name="line-62"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>setCurrentDirectory</span> <span class='hs-varop'>$</span> <span class='hs-varid'>libDir</span>
<a name="line-63"></a> <span class='hs-comment'>-- write the global results</span>
<a name="line-64"></a> <span class='hs-varid'>writeGlobalVHDLM</span>
<a name="line-65"></a> <span class='hs-comment'>-- change to systemName/vhdl</span>
<a name="line-66"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>setCurrentDirectory</span> <span class='hs-str'>".."</span>
<a name="line-67"></a> <span class='hs-comment'>-- call quartus if necessary</span>
<a name="line-68"></a> <span class='hs-varid'>callQuartus</span>
<a name="line-69"></a> <span class='hs-comment'>-- analyze with modelsim if necessary</span>
<a name="line-70"></a> <span class='hs-varid'>compile</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>isCompileModelsimSet</span>
<a name="line-71"></a> <span class='hs-varid'>when</span> <span class='hs-varid'>compile</span> <span class='hs-varid'>compileResultsModelsim</span>
<a name="line-72"></a> <span class='hs-comment'>-- go back to the original directory</span>
<a name="line-73"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>setCurrentDirectory</span> <span class='hs-layout'>(</span><span class='hs-str'>".."</span> <span class='hs-varop'></></span> <span class='hs-str'>".."</span><span class='hs-layout'>)</span>
<a name="line-74"></a>
<a name="line-75"></a><a name="writeGlobalVHDLM"></a><span class='hs-comment'>-- | Write the global traversing results (i.e. the library design file)</span>
<a name="line-76"></a><span class='hs-comment'>-- accumulated in the state of the monad</span>
<a name="line-77"></a><span class='hs-definition'>writeGlobalVHDLM</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>VHDLM</span> <span class='hs-conid'>()</span>
<a name="line-78"></a><span class='hs-definition'>writeGlobalVHDLM</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-79"></a> <span class='hs-varid'>gSysId</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>sid</span><span class='hs-varop'>.</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span>
<a name="line-80"></a> <span class='hs-varid'>debugMsg</span> <span class='hs-varop'>$</span> <span class='hs-str'>"Generating global system library for `"</span> <span class='hs-varop'>++</span> <span class='hs-varid'>gSysId</span> <span class='hs-varop'>++</span> <span class='hs-str'>"' ...\n"</span>
<a name="line-81"></a> <span class='hs-varid'>globalRes</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>globalRes</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span>
<a name="line-82"></a> <span class='hs-comment'>-- We can create the id unsafely because sysId was already checked in</span>
<a name="line-83"></a> <span class='hs-comment'>-- transSysDef2Ent</span>
<a name="line-84"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>libName</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>gSysId</span> <span class='hs-varop'>++</span> <span class='hs-str'>"_lib"</span>
<a name="line-85"></a> <span class='hs-varid'>libDesignFile</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genLibDesignFile</span> <span class='hs-varid'>globalRes</span>
<a name="line-86"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>writeDesignFile</span> <span class='hs-varid'>libDesignFile</span> <span class='hs-layout'>(</span><span class='hs-varid'>libName</span> <span class='hs-varop'>++</span> <span class='hs-str'>".vhd"</span><span class='hs-layout'>)</span>
<a name="line-87"></a>
<a name="line-88"></a>
<a name="line-89"></a><a name="writeLocalVHDLM"></a><span class='hs-comment'>-- | Traverse the netlist and write the local results (i.e. system design files)</span>
<a name="line-90"></a><span class='hs-definition'>writeLocalVHDLM</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>VHDLM</span> <span class='hs-conid'>()</span>
<a name="line-91"></a><span class='hs-definition'>writeLocalVHDLM</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-92"></a> <span class='hs-varid'>gSysDefVal</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>globalSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>global</span><span class='hs-layout'>)</span>
<a name="line-93"></a> <span class='hs-varid'>lSysDefVal</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>currSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>local</span><span class='hs-layout'>)</span>
<a name="line-94"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>lSysDefId</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>sid</span> <span class='hs-varid'>lSysDefVal</span>
<a name="line-95"></a> <span class='hs-varid'>debugMsg</span> <span class='hs-varop'>$</span> <span class='hs-str'>"Compiling system definition `"</span> <span class='hs-varop'>++</span> <span class='hs-varid'>lSysDefId</span> <span class='hs-varop'>++</span> <span class='hs-str'>"' ...\n"</span>
<a name="line-96"></a> <span class='hs-comment'>-- Obtain the netlist of the system definition </span>
<a name="line-97"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>nl</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>netlist</span> <span class='hs-varid'>lSysDefVal</span>
<a name="line-98"></a> <span class='hs-comment'>-- Traverse the netlist, and get the traversing results</span>
<a name="line-99"></a> <span class='hs-varid'>intOutsInfo</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>traverseVHDLM</span> <span class='hs-varid'>nl</span>
<a name="line-100"></a> <span class='hs-conid'>LocalTravResult</span> <span class='hs-varid'>decs</span> <span class='hs-varid'>stms</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>gets</span> <span class='hs-layout'>(</span><span class='hs-varid'>localRes</span><span class='hs-varop'>.</span><span class='hs-varid'>local</span><span class='hs-layout'>)</span>
<a name="line-101"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>finalLogic</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>logic</span> <span class='hs-varid'>lSysDefVal</span>
<a name="line-102"></a> <span class='hs-comment'>-- Obtain the entity declaration of the system and the VHDL identifiers</span>
<a name="line-103"></a> <span class='hs-comment'>-- of the output signals.</span>
<a name="line-104"></a> <span class='hs-varid'>entity</span><span class='hs-keyglyph'>@</span><span class='hs-layout'>(</span><span class='hs-conid'>EntityDec</span> <span class='hs-keyword'>_</span> <span class='hs-varid'>eIface</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transSysDef2Ent</span> <span class='hs-varid'>finalLogic</span> <span class='hs-varid'>lSysDefVal</span>
<a name="line-105"></a> <span class='hs-comment'>-- For each output signal, we need an assigment between its intermediate</span>
<a name="line-106"></a> <span class='hs-comment'>-- signal and the final output signal declared in the entity interface.</span>
<a name="line-107"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>outIds</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>mapFilter</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-layout'>(</span><span class='hs-conid'>IfaceSigDec</span> <span class='hs-varid'>id</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>id</span><span class='hs-layout'>)</span>
<a name="line-108"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-layout'>(</span><span class='hs-conid'>IfaceSigDec</span> <span class='hs-keyword'>_</span> <span class='hs-varid'>m</span> <span class='hs-keyword'>_</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>m</span> <span class='hs-varop'>==</span> <span class='hs-conid'>Out</span><span class='hs-layout'>)</span> <span class='hs-varid'>eIface</span>
<a name="line-109"></a> <span class='hs-varid'>outAssigns</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genOutAssigns</span> <span class='hs-varid'>outIds</span> <span class='hs-varid'>intOutsInfo</span>
<a name="line-110"></a> <span class='hs-varid'>finalRes</span> <span class='hs-keyglyph'>=</span> <span class='hs-conid'>LocalTravResult</span> <span class='hs-varid'>decs</span> <span class='hs-layout'>(</span><span class='hs-varid'>stms</span> <span class='hs-varop'>++</span> <span class='hs-varid'>outAssigns</span><span class='hs-layout'>)</span>
<a name="line-111"></a> <span class='hs-comment'>-- Finally, generate the design file</span>
<a name="line-112"></a> <span class='hs-varid'>sysDesignFile</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>genSysDesignFile</span> <span class='hs-layout'>(</span><span class='hs-varid'>sid</span> <span class='hs-varid'>gSysDefVal</span><span class='hs-layout'>)</span> <span class='hs-varid'>entity</span> <span class='hs-varid'>finalRes</span>
<a name="line-113"></a> <span class='hs-comment'>-- and write it to disk</span>
<a name="line-114"></a> <span class='hs-varid'>liftIO</span> <span class='hs-varop'>$</span> <span class='hs-varid'>writeDesignFile</span> <span class='hs-varid'>sysDesignFile</span> <span class='hs-layout'>(</span><span class='hs-varid'>lSysDefId</span> <span class='hs-varop'>++</span> <span class='hs-str'>".vhd"</span><span class='hs-layout'>)</span>
<a name="line-115"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>mapFilter</span> <span class='hs-varid'>f</span> <span class='hs-varid'>p</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>foldr</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-varid'>x</span> <span class='hs-varid'>ys</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>if</span> <span class='hs-varid'>p</span> <span class='hs-varid'>x</span> <span class='hs-keyword'>then</span> <span class='hs-layout'>(</span><span class='hs-varid'>f</span> <span class='hs-varid'>x</span><span class='hs-layout'>)</span><span class='hs-conop'>:</span><span class='hs-varid'>ys</span> <span class='hs-keyword'>else</span> <span class='hs-varid'>ys</span><span class='hs-layout'>)</span> <span class='hs-conid'>[]</span>
<a name="line-116"></a>
<a name="line-117"></a><a name="traverseVHDLM"></a><span class='hs-comment'>-- | Traverse the netlist of a System Definition, </span>
<a name="line-118"></a><span class='hs-comment'>-- returning the (implicit) final traversing state and a list</span>
<a name="line-119"></a><span class='hs-comment'>-- containing the 'IntSignalInfo' of each output of the system</span>
<a name="line-120"></a><span class='hs-definition'>traverseVHDLM</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>Netlist</span> <span class='hs-conid'>[]</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-keyglyph'>[</span><span class='hs-conid'>IntSignalInfo</span><span class='hs-keyglyph'>]</span>
<a name="line-121"></a><span class='hs-definition'>traverseVHDLM</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>traverseSEIO</span> <span class='hs-varid'>newVHDL</span> <span class='hs-varid'>defineVHDL</span>
<a name="line-122"></a>
<a name="line-123"></a><a name="newVHDL"></a><span class='hs-comment'>-- | \'new\' traversing function for the VHDL backend</span>
<a name="line-124"></a><span class='hs-definition'>newVHDL</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>NlNode</span> <span class='hs-conid'>NlSignal</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>NlNodeOut</span><span class='hs-layout'>,</span> <span class='hs-conid'>IntSignalInfo</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-125"></a><span class='hs-definition'>newVHDL</span> <span class='hs-varid'>node</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>case</span> <span class='hs-varid'>node</span> <span class='hs-keyword'>of</span>
<a name="line-126"></a> <span class='hs-comment'>-- FIXME: Skip the case, basing the generation of tags on</span>
<a name="line-127"></a> <span class='hs-comment'>-- outTags </span>
<a name="line-128"></a> <span class='hs-conid'>InPort</span> <span class='hs-varid'>id</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span> <span class='hs-varid'>vId</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transPortId2VHDL</span> <span class='hs-varid'>id</span>
<a name="line-129"></a> <span class='hs-varid'>return</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>InPortOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>vId</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-130"></a> <span class='hs-conid'>Proc</span> <span class='hs-varid'>pid</span> <span class='hs-varid'>proc</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>withProcC</span> <span class='hs-varid'>pid</span> <span class='hs-varop'>$</span> <span class='hs-keyword'>do</span>
<a name="line-131"></a> <span class='hs-comment'>-- Obtain the VHDL id of the process</span>
<a name="line-132"></a> <span class='hs-varid'>vpid</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transProcId2VHDL</span> <span class='hs-varid'>pid</span>
<a name="line-133"></a> <span class='hs-comment'>-- function to create an intermediate signal out of the process</span>
<a name="line-134"></a> <span class='hs-comment'>-- identifier and a string suffix</span>
<a name="line-135"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>procSuffSignal</span> <span class='hs-varid'>sigSuffix</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>unsafeIdAppend</span> <span class='hs-varid'>vpid</span> <span class='hs-varid'>sigSuffix</span>
<a name="line-136"></a> <span class='hs-comment'>-- Multiple output tags, add a numeric suffix specifying the output</span>
<a name="line-137"></a> <span class='hs-varid'>multOutTags</span> <span class='hs-keyglyph'>=</span>
<a name="line-138"></a> <span class='hs-varid'>zipWith</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-varid'>tag</span> <span class='hs-varid'>n</span> <span class='hs-keyglyph'>-></span> <span class='hs-layout'>(</span><span class='hs-varid'>tag</span><span class='hs-layout'>,</span> <span class='hs-varid'>procSuffSignal</span> <span class='hs-varop'>$</span> <span class='hs-varid'>outSuffix</span> <span class='hs-varop'>++</span> <span class='hs-varid'>show</span> <span class='hs-varid'>n</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span>
<a name="line-139"></a> <span class='hs-layout'>(</span><span class='hs-varid'>outTags</span> <span class='hs-varid'>node</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-num'>1</span><span class='hs-keyglyph'>::</span><span class='hs-conid'>Int</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>..</span><span class='hs-keyglyph'>]</span>
<a name="line-140"></a> <span class='hs-keyword'>case</span> <span class='hs-varid'>proc</span> <span class='hs-keyword'>of</span>
<a name="line-141"></a> <span class='hs-conid'>Const</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>ConstOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>procSuffSignal</span> <span class='hs-varid'>outSuffix</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-142"></a> <span class='hs-conid'>ZipWithNSY</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>ZipWithNSYOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>procSuffSignal</span> <span class='hs-varid'>outSuffix</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-143"></a> <span class='hs-conid'>ZipWithxSY</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>ZipWithxSYOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>procSuffSignal</span> <span class='hs-varid'>outSuffix</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-144"></a> <span class='hs-conid'>UnzipNSY</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-varid'>multOutTags</span>
<a name="line-145"></a> <span class='hs-conid'>UnzipxSY</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-varid'>multOutTags</span>
<a name="line-146"></a> <span class='hs-conid'>DelaySY</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>DelaySYOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>procSuffSignal</span> <span class='hs-varid'>outSuffix</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-147"></a> <span class='hs-conid'>SysIns</span> <span class='hs-keyword'>_</span> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span>
<a name="line-148"></a> <span class='hs-comment'>-- Note: Here we could use the name of the System outputs instead of</span>
<a name="line-149"></a> <span class='hs-comment'>-- instanceid_out_n but ... that could cause</span>
<a name="line-150"></a> <span class='hs-comment'>-- clashes with the oher signal names (we only check for the</span>
<a name="line-151"></a> <span class='hs-comment'>-- of the uniqueness of all process ids within a system when </span>
<a name="line-152"></a> <span class='hs-comment'>-- creating it). We could check for those clashes but it would be</span>
<a name="line-153"></a> <span class='hs-comment'>-- ineffective and ilogical.</span>
<a name="line-154"></a> <span class='hs-varid'>return</span> <span class='hs-varid'>multOutTags</span>
<a name="line-155"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>outSuffix</span> <span class='hs-keyglyph'>=</span> <span class='hs-str'>"_out"</span>
<a name="line-156"></a>
<a name="line-157"></a><a name="defineVHDL"></a><span class='hs-comment'>-- | \'define\' traversing function for the VHDL backend</span>
<a name="line-158"></a><span class='hs-definition'>defineVHDL</span> <span class='hs-keyglyph'>::</span> <span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>NlNodeOut</span><span class='hs-layout'>,</span> <span class='hs-conid'>IntSignalInfo</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span>
<a name="line-159"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>NlNode</span> <span class='hs-conid'>IntSignalInfo</span>
<a name="line-160"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-conid'>()</span>
<a name="line-161"></a><span class='hs-definition'>defineVHDL</span> <span class='hs-varid'>outs</span> <span class='hs-varid'>ins</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-162"></a> <span class='hs-keyword'>case</span> <span class='hs-layout'>(</span><span class='hs-varid'>outs</span><span class='hs-layout'>,</span><span class='hs-varid'>ins</span><span class='hs-layout'>)</span> <span class='hs-keyword'>of</span>
<a name="line-163"></a> <span class='hs-layout'>(</span><span class='hs-keyword'>_</span><span class='hs-layout'>,</span> <span class='hs-conid'>InPort</span> <span class='hs-keyword'>_</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>return</span> <span class='hs-conid'>()</span>
<a name="line-164"></a> <span class='hs-layout'>(</span><span class='hs-varid'>outs</span><span class='hs-layout'>,</span> <span class='hs-conid'>Proc</span> <span class='hs-varid'>pid</span> <span class='hs-varid'>proc</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>withProcC</span> <span class='hs-varid'>pid</span> <span class='hs-varop'>$</span> <span class='hs-keyword'>do</span>
<a name="line-165"></a> <span class='hs-comment'>-- We can unsafely transform the pid to a VHDL identifier because</span>
<a name="line-166"></a> <span class='hs-comment'>-- it was checked in newVHDL</span>
<a name="line-167"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>vPid</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>unsafeVHDLExtId</span> <span class='hs-varid'>pid</span>
<a name="line-168"></a> <span class='hs-keyword'>case</span> <span class='hs-layout'>(</span><span class='hs-varid'>outs</span><span class='hs-layout'>,</span> <span class='hs-varid'>proc</span><span class='hs-layout'>)</span> <span class='hs-keyword'>of</span>
<a name="line-169"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>ConstOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>intSig</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>,</span> <span class='hs-conid'>Const</span> <span class='hs-conid'>ProcVal</span><span class='hs-layout'>{</span><span class='hs-varid'>valAST</span><span class='hs-keyglyph'>=</span><span class='hs-varid'>ast</span><span class='hs-layout'>}</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-170"></a> <span class='hs-comment'>-- Generate a Signal declaration for the constant</span>
<a name="line-171"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>cons</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>expVal</span> <span class='hs-varid'>ast</span>
<a name="line-172"></a> <span class='hs-varid'>dec</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>withProcValC</span> <span class='hs-varid'>cons</span> <span class='hs-varop'>$</span> <span class='hs-varid'>transVHDLName2SigDec</span>
<a name="line-173"></a> <span class='hs-varid'>intSig</span> <span class='hs-layout'>(</span><span class='hs-varid'>expTyp</span> <span class='hs-varid'>ast</span><span class='hs-layout'>)</span> <span class='hs-layout'>(</span><span class='hs-conid'>Just</span> <span class='hs-varid'>cons</span><span class='hs-layout'>)</span>
<a name="line-174"></a> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>dec</span>
<a name="line-175"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>ZipWithNSYOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>intOut</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>,</span> <span class='hs-conid'>ZipWithNSY</span> <span class='hs-varid'>f</span> <span class='hs-varid'>intIns</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-176"></a> <span class='hs-comment'>-- Translate the zipWithN process to a block</span>
<a name="line-177"></a> <span class='hs-comment'>-- and get the declaration of its output signal</span>
<a name="line-178"></a> <span class='hs-layout'>(</span><span class='hs-varid'>block</span><span class='hs-layout'>,</span> <span class='hs-varid'>dec</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transZipWithN2Block</span> <span class='hs-varid'>vPid</span> <span class='hs-varid'>intIns</span> <span class='hs-layout'>(</span><span class='hs-varid'>tpfloc</span> <span class='hs-varid'>f</span><span class='hs-layout'>)</span> <span class='hs-layout'>(</span><span class='hs-varid'>tast</span> <span class='hs-varid'>f</span><span class='hs-layout'>)</span> <span class='hs-varid'>intOut</span>
<a name="line-179"></a> <span class='hs-varid'>addStm</span> <span class='hs-varop'>$</span> <span class='hs-conid'>CSBSm</span> <span class='hs-varid'>block</span>
<a name="line-180"></a> <span class='hs-comment'>-- Generate a signal declaration for the resulting signal</span>
<a name="line-181"></a> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>dec</span>
<a name="line-182"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>ZipWithxSYOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>intOut</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>,</span> <span class='hs-conid'>ZipWithxSY</span> <span class='hs-varid'>f</span> <span class='hs-varid'>intIns</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-183"></a> <span class='hs-comment'>-- Translate the zipWithx process to a block</span>
<a name="line-184"></a> <span class='hs-comment'>-- and get the declaration of its output signal</span>
<a name="line-185"></a> <span class='hs-layout'>(</span><span class='hs-varid'>block</span><span class='hs-layout'>,</span> <span class='hs-varid'>dec</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transZipWithx2Block</span> <span class='hs-varid'>vPid</span> <span class='hs-varid'>intIns</span> <span class='hs-layout'>(</span><span class='hs-varid'>tpfloc</span> <span class='hs-varid'>f</span><span class='hs-layout'>)</span> <span class='hs-layout'>(</span><span class='hs-varid'>tast</span> <span class='hs-varid'>f</span><span class='hs-layout'>)</span> <span class='hs-varid'>intOut</span>
<a name="line-186"></a> <span class='hs-varid'>addStm</span> <span class='hs-varop'>$</span> <span class='hs-conid'>CSBSm</span> <span class='hs-varid'>block</span>
<a name="line-187"></a> <span class='hs-comment'>-- Generate a signal declaration for the resulting signal</span>
<a name="line-188"></a> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>dec</span>
<a name="line-189"></a> <span class='hs-layout'>(</span><span class='hs-varid'>intOuts</span><span class='hs-layout'>,</span> <span class='hs-conid'>UnzipNSY</span> <span class='hs-varid'>outTypes</span> <span class='hs-keyword'>_</span> <span class='hs-varid'>intIn</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-190"></a> <span class='hs-comment'>-- Translate the zipWithNSY process to a block</span>
<a name="line-191"></a> <span class='hs-comment'>-- and get the declaration of its output signal</span>
<a name="line-192"></a> <span class='hs-layout'>(</span><span class='hs-varid'>block</span><span class='hs-layout'>,</span> <span class='hs-varid'>decs</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transUnzipNSY2Block</span> <span class='hs-varid'>vPid</span> <span class='hs-varid'>intIn</span> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-varid'>snd</span> <span class='hs-varid'>intOuts</span><span class='hs-layout'>)</span> <span class='hs-varid'>outTypes</span>
<a name="line-193"></a> <span class='hs-varid'>addStm</span> <span class='hs-varop'>$</span> <span class='hs-conid'>CSBSm</span> <span class='hs-varid'>block</span>
<a name="line-194"></a> <span class='hs-comment'>-- Generate a signal declaration for the resulting signals</span>
<a name="line-195"></a> <span class='hs-varid'>mapM_</span> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>decs</span>
<a name="line-196"></a> <span class='hs-layout'>(</span><span class='hs-varid'>intOuts</span><span class='hs-layout'>,</span> <span class='hs-conid'>UnzipxSY</span> <span class='hs-varid'>typ</span> <span class='hs-varid'>size</span> <span class='hs-keyword'>_</span> <span class='hs-varid'>intIn</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-197"></a> <span class='hs-comment'>-- Translate the UnzipxSY process to a block</span>
<a name="line-198"></a> <span class='hs-comment'>-- and get the declaration of its output signal</span>
<a name="line-199"></a> <span class='hs-layout'>(</span><span class='hs-varid'>block</span><span class='hs-layout'>,</span> <span class='hs-varid'>decs</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transUnzipxSY2Block</span> <span class='hs-varid'>vPid</span> <span class='hs-varid'>intIn</span> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-varid'>snd</span> <span class='hs-varid'>intOuts</span><span class='hs-layout'>)</span> <span class='hs-varid'>typ</span> <span class='hs-varid'>size</span>
<a name="line-200"></a> <span class='hs-varid'>addStm</span> <span class='hs-varop'>$</span> <span class='hs-conid'>CSBSm</span> <span class='hs-varid'>block</span>
<a name="line-201"></a> <span class='hs-comment'>-- Generate a signal declaration for the resulting signals</span>
<a name="line-202"></a> <span class='hs-varid'>mapM_</span> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>decs</span>
<a name="line-203"></a> <span class='hs-layout'>(</span><span class='hs-keyglyph'>[</span><span class='hs-layout'>(</span><span class='hs-conid'>DelaySYOut</span><span class='hs-layout'>,</span> <span class='hs-varid'>intOut</span><span class='hs-layout'>)</span><span class='hs-keyglyph'>]</span><span class='hs-layout'>,</span> <span class='hs-conid'>DelaySY</span> <span class='hs-varid'>initExp</span> <span class='hs-varid'>intIn</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-204"></a> <span class='hs-comment'>-- Translate the delay process to a block</span>
<a name="line-205"></a> <span class='hs-comment'>-- and get the declaration of its output signal</span>
<a name="line-206"></a> <span class='hs-layout'>(</span><span class='hs-varid'>block</span><span class='hs-layout'>,</span> <span class='hs-varid'>dec</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transDelay2Block</span> <span class='hs-varid'>vPid</span> <span class='hs-varid'>intIn</span> <span class='hs-layout'>(</span><span class='hs-varid'>valAST</span> <span class='hs-varid'>initExp</span><span class='hs-layout'>)</span> <span class='hs-varid'>intOut</span>
<a name="line-207"></a> <span class='hs-varid'>addStm</span> <span class='hs-varop'>$</span> <span class='hs-conid'>CSBSm</span> <span class='hs-varid'>block</span>
<a name="line-208"></a> <span class='hs-comment'>-- Generate a signal declaration for the resulting delayed signal</span>
<a name="line-209"></a> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>dec</span>
<a name="line-210"></a>
<a name="line-211"></a> <span class='hs-layout'>(</span><span class='hs-varid'>intOuts</span><span class='hs-layout'>,</span> <span class='hs-conid'>SysIns</span> <span class='hs-varid'>pSys</span> <span class='hs-varid'>intIns</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-keyword'>do</span>
<a name="line-212"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>parentSysRef</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>unPrimSysDef</span> <span class='hs-varid'>pSys</span>
<a name="line-213"></a> <span class='hs-varid'>parentSysVal</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>readURef</span> <span class='hs-varid'>parentSysRef</span>
<a name="line-214"></a> <span class='hs-varid'>parentLogic</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>logic</span> <span class='hs-varid'>parentSysVal</span>
<a name="line-215"></a> <span class='hs-varid'>parentInIface</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>iIface</span> <span class='hs-varid'>parentSysVal</span>
<a name="line-216"></a> <span class='hs-varid'>parentOutIface</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>oIface</span> <span class='hs-varid'>parentSysVal</span>
<a name="line-217"></a> <span class='hs-varid'>typedOuts</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>zipWith</span> <span class='hs-layout'>(</span><span class='hs-keyglyph'>\</span><span class='hs-layout'>(</span><span class='hs-keyword'>_</span><span class='hs-layout'>,</span> <span class='hs-varid'>t</span><span class='hs-layout'>)</span> <span class='hs-layout'>(</span><span class='hs-keyword'>_</span><span class='hs-layout'>,</span> <span class='hs-varid'>int</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'>-></span> <span class='hs-layout'>(</span><span class='hs-varid'>int</span><span class='hs-layout'>,</span><span class='hs-varid'>t</span><span class='hs-layout'>)</span><span class='hs-layout'>)</span> <span class='hs-varid'>parentOutIface</span>
<a name="line-218"></a> <span class='hs-varid'>intOuts</span>
<a name="line-219"></a> <span class='hs-varid'>parentId</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>sid</span> <span class='hs-varid'>parentSysVal</span>
<a name="line-220"></a> <span class='hs-comment'>-- Translate the instance to a component instantiation </span>
<a name="line-221"></a> <span class='hs-comment'>-- and get the declaration of the output signals</span>
<a name="line-222"></a> <span class='hs-layout'>(</span><span class='hs-varid'>mCompIns</span><span class='hs-layout'>,</span> <span class='hs-varid'>decs</span><span class='hs-layout'>)</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>transSysIns2CompIns</span> <span class='hs-varid'>parentLogic</span>
<a name="line-223"></a> <span class='hs-varid'>vPid</span>
<a name="line-224"></a> <span class='hs-varid'>intIns</span>
<a name="line-225"></a> <span class='hs-varid'>typedOuts</span>
<a name="line-226"></a> <span class='hs-varid'>parentId</span>
<a name="line-227"></a> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-varid'>fst</span> <span class='hs-varid'>parentInIface</span><span class='hs-layout'>)</span>
<a name="line-228"></a> <span class='hs-layout'>(</span><span class='hs-varid'>map</span> <span class='hs-varid'>fst</span> <span class='hs-varid'>parentOutIface</span><span class='hs-layout'>)</span>
<a name="line-229"></a> <span class='hs-varid'>when</span> <span class='hs-layout'>(</span><span class='hs-varid'>isJust</span> <span class='hs-varid'>mCompIns</span><span class='hs-layout'>)</span> <span class='hs-layout'>(</span><span class='hs-varid'>addStm</span> <span class='hs-varop'>$</span> <span class='hs-conid'>CSISm</span> <span class='hs-varop'>$</span> <span class='hs-varid'>fromJust</span> <span class='hs-varid'>mCompIns</span><span class='hs-layout'>)</span>
<a name="line-230"></a> <span class='hs-comment'>-- Generate a signal declaration for each of the resulting signals</span>
<a name="line-231"></a> <span class='hs-varid'>mapM_</span> <span class='hs-varid'>addSigDec</span> <span class='hs-varid'>decs</span>
<a name="line-232"></a>
<a name="line-233"></a><span class='hs-comment'>-- Othewise there is a problem of inconsisten tags</span>
<a name="line-234"></a> <span class='hs-keyword'>_</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>intError</span> <span class='hs-str'>"ForSyDe.Backend.VHDL.Traverse.defineVHDL"</span> <span class='hs-conid'>InconsOutTag</span>
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