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<pre><a name="line-1"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span>
<a name="line-2"></a><span class='hs-comment'>-- |</span>
<a name="line-3"></a><span class='hs-comment'>-- Module : ForSyDe.Backend.VHDL</span>
<a name="line-4"></a><span class='hs-comment'>-- Copyright : (c) SAM Group, KTH/ICT/ECS 2007-2008</span>
<a name="line-5"></a><span class='hs-comment'>-- License : BSD-style (see the file LICENSE)</span>
<a name="line-6"></a><span class='hs-comment'>-- </span>
<a name="line-7"></a><span class='hs-comment'>-- Maintainer : forsyde-dev@ict.kth.se</span>
<a name="line-8"></a><span class='hs-comment'>-- Stability : experimental</span>
<a name="line-9"></a><span class='hs-comment'>-- Portability : portable</span>
<a name="line-10"></a><span class='hs-comment'>--</span>
<a name="line-11"></a><span class='hs-comment'>-- This module provides the VHDL backend of ForSyDe's embedded compiler</span>
<a name="line-12"></a><span class='hs-comment'>--</span>
<a name="line-13"></a><span class='hs-comment'>-----------------------------------------------------------------------------</span>
<a name="line-14"></a><span class='hs-keyword'>module</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span>
<a name="line-15"></a> <span class='hs-layout'>(</span><span class='hs-varid'>writeVHDL</span><span class='hs-layout'>,</span>
<a name="line-16"></a> <span class='hs-varid'>writeVHDLOps</span><span class='hs-layout'>,</span>
<a name="line-17"></a> <span class='hs-varid'>writeAndModelsimVHDL</span><span class='hs-layout'>,</span>
<a name="line-18"></a> <span class='hs-varid'>writeAndModelsimVHDLOps</span><span class='hs-layout'>,</span>
<a name="line-19"></a> <span class='hs-conid'>VHDLOps</span><span class='hs-layout'>(</span><span class='hs-keyglyph'>..</span><span class='hs-layout'>)</span><span class='hs-layout'>,</span>
<a name="line-20"></a> <span class='hs-conid'>QuartusOps</span><span class='hs-layout'>(</span><span class='hs-keyglyph'>..</span><span class='hs-layout'>)</span><span class='hs-layout'>,</span>
<a name="line-21"></a> <span class='hs-conid'>QuartusAction</span><span class='hs-layout'>(</span><span class='hs-keyglyph'>..</span><span class='hs-layout'>)</span><span class='hs-layout'>,</span>
<a name="line-22"></a> <span class='hs-varid'>checkSynthesisQuartus</span><span class='hs-layout'>,</span>
<a name="line-23"></a> <span class='hs-conid'>VHDLDebugLevel</span><span class='hs-layout'>(</span><span class='hs-keyglyph'>..</span><span class='hs-layout'>)</span><span class='hs-layout'>,</span>
<a name="line-24"></a> <span class='hs-conid'>VHDLRecursivity</span><span class='hs-layout'>(</span><span class='hs-keyglyph'>..</span><span class='hs-layout'>)</span><span class='hs-layout'>,</span>
<a name="line-25"></a> <span class='hs-varid'>defaultVHDLOps</span><span class='hs-layout'>)</span> <span class='hs-keyword'>where</span>
<a name="line-26"></a>
<a name="line-27"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>Control</span><span class='hs-varop'>.</span><span class='hs-conid'>Monad</span><span class='hs-varop'>.</span><span class='hs-conid'>State</span> <span class='hs-layout'>(</span><span class='hs-varid'>evalStateT</span><span class='hs-layout'>)</span>
<a name="line-28"></a><span class='hs-keyword'>import</span> <span class='hs-keyword'>qualified</span> <span class='hs-conid'>Language</span><span class='hs-varop'>.</span><span class='hs-conid'>Haskell</span><span class='hs-varop'>.</span><span class='hs-conid'>TH</span> <span class='hs-keyword'>as</span> <span class='hs-conid'>TH</span>
<a name="line-29"></a>
<a name="line-30"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>SysFun</span>
<a name="line-31"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>ForSyDeErr</span>
<a name="line-32"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>OSharing</span> <span class='hs-layout'>(</span><span class='hs-varid'>readURef</span><span class='hs-layout'>)</span>
<a name="line-33"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>System</span><span class='hs-varop'>.</span><span class='hs-conid'>SysDef</span>
<a name="line-34"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Traverse</span>
<a name="line-35"></a><span class='hs-keyword'>import</span> <span class='hs-conid'>ForSyDe</span><span class='hs-varop'>.</span><span class='hs-conid'>Backend</span><span class='hs-varop'>.</span><span class='hs-conid'>VHDL</span><span class='hs-varop'>.</span><span class='hs-conid'>Modelsim</span>
<a name="line-36"></a>
<a name="line-37"></a><a name="writeVHDL"></a><span class='hs-comment'>-- | Given a System Definition whose name is a valid VHDL _basic_ identifier </span>
<a name="line-38"></a><span class='hs-comment'>-- (call it \"A\") generate @A.vhd@ in current working directory using </span>
<a name="line-39"></a><span class='hs-comment'>-- default compilation options.</span>
<a name="line-40"></a><span class='hs-comment'>-- Imp: the input and output signal names of A must be valid VHDL identifiers</span>
<a name="line-41"></a><span class='hs-comment'>-- (basic or extended) and different to @clk@ and @reset@</span>
<a name="line-42"></a><span class='hs-comment'>-- which are reserved for the main clock and reset signals</span>
<a name="line-43"></a><span class='hs-definition'>writeVHDL</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>SysDef</span> <span class='hs-varid'>a</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>IO</span> <span class='hs-conid'>()</span>
<a name="line-44"></a><span class='hs-definition'>writeVHDL</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>writeVHDLOps</span> <span class='hs-varid'>defaultVHDLOps</span>
<a name="line-45"></a>
<a name="line-46"></a><a name="writeVHDLOps"></a><span class='hs-comment'>-- | 'writeVHDL'-alternative which allows setting VHDL compilation options.</span>
<a name="line-47"></a><span class='hs-definition'>writeVHDLOps</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>VHDLOps</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>SysDef</span> <span class='hs-varid'>a</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>IO</span> <span class='hs-conid'>()</span>
<a name="line-48"></a><span class='hs-definition'>writeVHDLOps</span> <span class='hs-varid'>ops</span> <span class='hs-varid'>sysDef</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-49"></a> <span class='hs-comment'>-- initiate the compilation State</span>
<a name="line-50"></a> <span class='hs-keyword'>let</span> <span class='hs-varid'>sinit</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>initVHDLTravST</span> <span class='hs-varop'>$</span> <span class='hs-layout'>(</span><span class='hs-varid'>readURef</span><span class='hs-varop'>.</span><span class='hs-varid'>unPrimSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>unSysDef</span><span class='hs-layout'>)</span> <span class='hs-varid'>sysDef</span>
<a name="line-51"></a> <span class='hs-comment'>-- Compile the code</span>
<a name="line-52"></a> <span class='hs-varid'>res</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>runErrorT</span> <span class='hs-varop'>$</span> <span class='hs-varid'>evalStateT</span> <span class='hs-layout'>(</span><span class='hs-varid'>setVHDLOps</span> <span class='hs-varid'>ops</span> <span class='hs-varop'>>></span> <span class='hs-varid'>writeVHDLM</span><span class='hs-layout'>)</span> <span class='hs-varid'>sinit</span>
<a name="line-53"></a> <span class='hs-comment'>-- Check if the compilation went well and print an error in case it didn't</span>
<a name="line-54"></a> <span class='hs-varid'>either</span> <span class='hs-varid'>printVHDLError</span> <span class='hs-varid'>return</span> <span class='hs-varid'>res</span>
<a name="line-55"></a>
<a name="line-56"></a>
<a name="line-57"></a>
<a name="line-58"></a><a name="writeAndModelsimVHDL"></a><span class='hs-comment'>-- | Generate a function which, given a system definition and some simulation</span>
<a name="line-59"></a><span class='hs-comment'>-- stimuli:</span>
<a name="line-60"></a><span class='hs-comment'>-- </span>
<a name="line-61"></a><span class='hs-comment'>-- (1) Writes a VHDL model of the system </span>
<a name="line-62"></a><span class='hs-comment'>-- </span>
<a name="line-63"></a><span class='hs-comment'>-- (2) Simulates the VHDL model with Modelsim getting the results back to Haskell</span>
<a name="line-64"></a><span class='hs-definition'>writeAndModelsimVHDL</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>SysFunToIOSimFun</span> <span class='hs-varid'>sysF</span> <span class='hs-varid'>simF</span> <span class='hs-keyglyph'>=></span>
<a name="line-65"></a> <span class='hs-conid'>Maybe</span> <span class='hs-conid'>Int</span> <span class='hs-comment'>-- ^ Number of cycles to simulate</span>
<a name="line-66"></a> <span class='hs-comment'>-- if 'Nothing' the number will be determined</span>
<a name="line-67"></a> <span class='hs-comment'>-- by the length of the input stimulti.</span>
<a name="line-68"></a> <span class='hs-comment'>-- Useful when the system to simulate doesn't</span>
<a name="line-69"></a> <span class='hs-comment'>-- have inputs or the inputs provided are </span>
<a name="line-70"></a> <span class='hs-comment'>-- infinite</span>
<a name="line-71"></a> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>SysDef</span> <span class='hs-varid'>sysF</span> <span class='hs-comment'>-- ^ system definition to simulate</span>
<a name="line-72"></a> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>simF</span>
<a name="line-73"></a><span class='hs-definition'>writeAndModelsimVHDL</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>writeAndModelsimVHDLOps</span> <span class='hs-varid'>defaultVHDLOps</span>
<a name="line-74"></a>
<a name="line-75"></a>
<a name="line-76"></a><a name="writeAndModelsimVHDLOps"></a><span class='hs-comment'>-- | 'VHDLOps'-alternative of 'writeAndModelsimVHDL', note that</span>
<a name="line-77"></a><span class='hs-comment'>-- compileModelSim will implicitly be set to True</span>
<a name="line-78"></a><span class='hs-definition'>writeAndModelsimVHDLOps</span> <span class='hs-keyglyph'>::</span> <span class='hs-conid'>SysFunToIOSimFun</span> <span class='hs-varid'>sysF</span> <span class='hs-varid'>simF</span> <span class='hs-keyglyph'>=></span>
<a name="line-79"></a> <span class='hs-conid'>VHDLOps</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>Maybe</span> <span class='hs-conid'>Int</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>SysDef</span> <span class='hs-varid'>sysF</span> <span class='hs-keyglyph'>-></span> <span class='hs-varid'>simF</span>
<a name="line-80"></a><span class='hs-definition'>writeAndModelsimVHDLOps</span> <span class='hs-varid'>ops</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>sysDef</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>fromTHStrSimFun</span> <span class='hs-varid'>simIO</span> <span class='hs-conid'>[]</span>
<a name="line-81"></a> <span class='hs-keyword'>where</span> <span class='hs-varid'>sinit</span> <span class='hs-keyglyph'>=</span> <span class='hs-varid'>initVHDLTravST</span> <span class='hs-varop'>$</span> <span class='hs-layout'>(</span><span class='hs-varid'>readURef</span><span class='hs-varop'>.</span><span class='hs-varid'>unPrimSysDef</span><span class='hs-varop'>.</span><span class='hs-varid'>unSysDef</span><span class='hs-layout'>)</span> <span class='hs-varid'>sysDef</span>
<a name="line-82"></a> <span class='hs-varid'>simVHDLM</span> <span class='hs-keyglyph'>::</span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>TH</span><span class='hs-varop'>.</span><span class='hs-conid'>Exp</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>VHDLM</span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>String</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span>
<a name="line-83"></a> <span class='hs-varid'>simVHDLM</span> <span class='hs-varid'>stimuli</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-84"></a> <span class='hs-varid'>setVHDLOps</span> <span class='hs-varid'>ops</span><span class='hs-layout'>{</span><span class='hs-varid'>compileModelsim</span><span class='hs-keyglyph'>=</span><span class='hs-conid'>True</span><span class='hs-layout'>}</span>
<a name="line-85"></a> <span class='hs-varid'>writeVHDLM</span>
<a name="line-86"></a> <span class='hs-varid'>executeTestBenchModelsim</span> <span class='hs-varid'>mCycles</span> <span class='hs-varid'>stimuli</span>
<a name="line-87"></a> <span class='hs-varid'>simIO</span> <span class='hs-keyglyph'>::</span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>TH</span><span class='hs-varop'>.</span><span class='hs-conid'>Exp</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span> <span class='hs-keyglyph'>-></span> <span class='hs-conid'>IO</span> <span class='hs-keyglyph'>[</span><span class='hs-keyglyph'>[</span><span class='hs-conid'>String</span><span class='hs-keyglyph'>]</span><span class='hs-keyglyph'>]</span>
<a name="line-88"></a> <span class='hs-varid'>simIO</span> <span class='hs-varid'>stimuli</span> <span class='hs-keyglyph'>=</span> <span class='hs-keyword'>do</span>
<a name="line-89"></a> <span class='hs-varid'>res</span> <span class='hs-keyglyph'><-</span> <span class='hs-varid'>runErrorT</span> <span class='hs-varop'>$</span> <span class='hs-varid'>evalStateT</span> <span class='hs-layout'>(</span><span class='hs-varid'>simVHDLM</span> <span class='hs-varid'>stimuli</span><span class='hs-layout'>)</span> <span class='hs-varid'>sinit</span>
<a name="line-90"></a> <span class='hs-varid'>either</span> <span class='hs-varid'>printVHDLError</span> <span class='hs-varid'>return</span> <span class='hs-varid'>res</span>
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