/* structural SystemC generated by gnetlist */ /* WARNING: This is a generated file, edits */ /* made here will be lost next time */ /* you run gnetlist! */ /* Id ........gnet-systemc.scm (04/09/2003) */ /* Source...../home/geda/gnet-systemc.scm */ /* Revision...0.3 (23/09/2003) */ /* Author.....Jaume Masip */ #include "systemc.h" #include "CAPACITOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "CAPACITOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "NPN_TRANSISTOR.h" #include "CAPACITOR.h" #include "directive.h" #include "include.h" #include "model.h" #include "VOLTAGE_SOURCE.h" #include "vsin.h" #include "CAPACITOR.h" #include "CAPACITOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "RESISTOR.h" #include "NPN_TRANSISTOR.h" SC_MODULE (not found) { /* Port directions begin here */ /* Wires from the design */ sc_signal<0> unnamed_net2; sc_signal<0> Vbase2; sc_signal<0> Vem2; sc_signal<0> Vout; sc_signal<0> VColl2; sc_signal<0> GND; sc_signal<0> Vcc; sc_signal<0> Vin; sc_signal<0> unnamed_net1; sc_signal<0> Vbase1; sc_signal<0> Vem1; sc_signal<0> Vcoll1; /* Package instantiations */ CAPACITOR C2; RESISTOR R4; RESISTOR R3; RESISTOR R8; CAPACITOR CE2; RESISTOR RE2; RESISTOR RC1; NPN_TRANSISTOR Q2; CAPACITOR C1; directive A3; include A2; model A1; VOLTAGE_SOURCE VCC; vsin Vinput; CAPACITOR CE1; CAPACITOR Cout; RESISTOR RL; RESISTOR RC2; RESISTOR RE1; RESISTOR R2; RESISTOR R1; RESISTOR R5; NPN_TRANSISTOR Q1; SC_CTOR(not found): C2("C2"), R4("R4"), R3("R3"), R8("R8"), CE2("CE2"), RE2("RE2"), RC1("RC1"), Q2("Q2"), C1("C1"), A3("A3"), A2("A2"), A1("A1"), VCC("VCC"), Vinput("Vinput"), CE1("CE1"), Cout("Cout"), RL("RL"), RC2("RC2"), RE1("RE1"), R2("R2"), R1("R1"), R5("R5"), Q1("Q1") { C2.1(unnamed_net2); C2.2(Vbase2); R4.2(Vbase2); R4.1(GND); R3.2(Vcc); R3.1(Vbase2); R8.2(unnamed_net2); R8.1(Vcoll1); CE2.1(GND); CE2.2(Vem2); RE2.2(Vem2); RE2.1(GND); RC1.2(Vcc); RC1.1(Vcoll1); Q2.3(VColl2); Q2.1(Vem2); Q2.2(Vbase2); C1.1(unnamed_net1); C1.2(Vbase1); VCC.1(Vcc); VCC.2(GND); Vinput.1(Vin); Vinput.2(GND); CE1.1(GND); CE1.2(Vem1); Cout.1(VColl2); Cout.2(Vout); RL.2(Vout); RL.1(GND); RC2.2(Vcc); RC2.1(VColl2); RE1.2(Vem1); RE1.1(GND); R2.2(Vbase1); R2.1(GND); R1.2(Vcc); R1.1(Vbase1); R5.2(unnamed_net1); R5.1(Vin); Q1.3(Vcoll1); Q1.1(Vem1); Q1.2(Vbase1); } };