-- Structural VAMS generated by gnetlist
-- Secondary unit

ARCHITECTURE default_architecture OF default_entity IS
	unknown unnamed_net2 	:  unknown;
	unknown Vbase2 	:  unknown;
	unknown Vem2 	:  unknown;
	unknown Vout 	:  unknown;
	unknown VColl2 	:  unknown;
	unknown GND 	:  unknown;
	unknown Vcc 	:  unknown;
	unknown Vin 	:  unknown;
	unknown unnamed_net1 	:  unknown;
	unknown Vbase1 	:  unknown;
	unknown Vem1 	:  unknown;
	unknown Vcoll1 	:  unknown;
BEGIN
-- Architecture statement part
 
  C2 : ENTITY CAPACITOR
	GENERIC MAP (
			symversion => 0.1, 
			device => CAPACITOR, 
			value => 2.2uF)
	PORT MAP (	1 => unnamed_net2,
			2 => Vbase2);
 
  R4 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 2.8K)
	PORT MAP (	2 => Vbase2,
			1 => GND);
 
  R3 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 28K)
	PORT MAP (	2 => Vcc,
			1 => Vbase2);
 
  R8 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 1)
	PORT MAP (	2 => unnamed_net2,
			1 => Vcoll1);
 
  CE2 : ENTITY CAPACITOR
	GENERIC MAP (
			symversion => 0.1, 
			device => CAPACITOR, 
			value => 1pF)
	PORT MAP (	1 => GND,
			2 => Vem2);
 
  RE2 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 100)
	PORT MAP (	2 => Vem2,
			1 => GND);
 
  RC1 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 3.3K)
	PORT MAP (	2 => Vcc,
			1 => Vcoll1);
 
  Q2 : ENTITY NPN_TRANSISTOR
	GENERIC MAP (
			device => NPN_TRANSISTOR, 
			model-name => 2N3904)
	PORT MAP (	3 => VColl2,
			1 => Vem2,
			2 => Vbase2);
 
  C1 : ENTITY CAPACITOR
	GENERIC MAP (
			symversion => 0.1, 
			device => CAPACITOR, 
			value => 2.2uF)
	PORT MAP (	1 => unnamed_net1,
			2 => Vbase1);
 
  A3 : ENTITY directive
	GENERIC MAP (
			device => directive, 
			value => .options TEMP=25)
;
 
  A2 : ENTITY include
	GENERIC MAP (
			device => include, 
			file => Simulation.cmd)
;
 
  A1 : ENTITY model
	GENERIC MAP (
			device => model, 
			file => ./models/2N3904.mod, 
			model-name => 2N3904)
;
 
  VCC : ENTITY VOLTAGE_SOURCE
	GENERIC MAP (
			footprint => none, 
			device => VOLTAGE_SOURCE, 
			value => DC 15V)
	PORT MAP (	1 => Vcc,
			2 => GND);
 
  Vinput : ENTITY vsin
	GENERIC MAP (
			footprint => none, 
			device => vsin, 
			value => DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
	PORT MAP (	1 => Vin,
			2 => GND);
 
  CE1 : ENTITY CAPACITOR
	GENERIC MAP (
			symversion => 0.1, 
			device => CAPACITOR, 
			value => 1pF)
	PORT MAP (	1 => GND,
			2 => Vem1);
 
  Cout : ENTITY CAPACITOR
	GENERIC MAP (
			symversion => 0.1, 
			device => CAPACITOR, 
			value => 2.2uF)
	PORT MAP (	1 => VColl2,
			2 => Vout);
 
  RL : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 100K)
	PORT MAP (	2 => Vout,
			1 => GND);
 
  RC2 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 1K)
	PORT MAP (	2 => Vcc,
			1 => VColl2);
 
  RE1 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 100)
	PORT MAP (	2 => Vem1,
			1 => GND);
 
  R2 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 2K)
	PORT MAP (	2 => Vbase1,
			1 => GND);
 
  R1 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 28K)
	PORT MAP (	2 => Vcc,
			1 => Vbase1);
 
  R5 : ENTITY RESISTOR
	GENERIC MAP (
			device => RESISTOR, 
			value => 10)
	PORT MAP (	2 => unnamed_net1,
			1 => Vin);
 
  Q1 : ENTITY NPN_TRANSISTOR
	GENERIC MAP (
			device => NPN_TRANSISTOR, 
			model-name => 2N3904)
	PORT MAP (	3 => Vcoll1,
			1 => Vem1,
			2 => Vbase1);
END ARCHITECTURE default_architecture;