/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire Vdd1 ;
wire GND ;
wire LVH ;
wire i ;
wire p ;
wire m ;

/* continuous assignments */

/* Package instantiations */
model A1 (     );

CAPACITOR Cm ( 
    .\1  ( m ),
    .\2  ( GND )
    );

CAPACITOR Cp ( 
    .\1  ( p ),
    .\2  ( GND )
    );

RESISTOR Rlp ( 
    .\2  ( Vdd1 ),
    .\1  ( p )
    );

RESISTOR Rlm ( 
    .\2  ( GND ),
    .\1  ( m )
    );

VOLTAGE_SOURCE Vdd ( 
    .\1  ( Vdd1 ),
    .\2  ( GND )
    );

vpulse V1 ( 
    .\1  ( i ),
    .\2  ( GND )
    );

RESISTOR Rt ( 
    .\2  ( m ),
    .\1  ( p )
    );

RESISTOR Rb ( 
    .\2  ( LVH ),
    .\1  ( GND )
    );

PMOS_TRANSISTOR M1 ( 
    .S ( Vdd1 ),
    .B ( Vdd1 ),
    .D ( LVH ),
    .G ( LVH )
    );

LVD X1 ( 
    .\4  ( m ),
    .\5  ( p ),
    .\1  ( i ),
    .\3  ( LVH ),
    .\2  ( GND ),
    .\6  ( Vdd1 ),
    .\7  ( GND )
    );

endmodule