/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire minusin_slot4_pin13_b ;
wire plusin_slot4_pin12_a ;
wire minusin_slot3_pin_b ;
wire plusin_slot3_pin10_a ;
wire minusin_slot2_pin6_b ;
wire plusin_slot2_pin5_a ;
wire samenet_output_c ;
wire minusin_slot1_pin_b ;
wire plusin_slot1_pin3_a ;

/* continuous assignments */

/* Package instantiations */
LM324 U1 ( 
    .\3  ( plusin_slot1_pin3_a ),
    .\2  ( minusin_slot1_pin_b ),
    .\1  ( samenet_output_c ),
    .\5  ( plusin_slot2_pin5_a ),
    .\6  ( minusin_slot2_pin6_b ),
    .\7  ( samenet_output_c ),
    .\10  ( plusin_slot3_pin10_a ),
    .\9  ( minusin_slot3_pin_b ),
    .\8  ( samenet_output_c ),
    .\12  ( plusin_slot4_pin12_a ),
    .\13  ( minusin_slot4_pin13_b ),
    .\14  ( samenet_output_c )
    );

endmodule