/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire unnamed_net2 ;
wire Vbase2 ;
wire Vem2 ;
wire Vout ;
wire VColl2 ;
wire GND ;
wire Vcc ;
wire Vin ;
wire unnamed_net1 ;
wire Vbase1 ;
wire Vem1 ;
wire Vcoll1 ;

/* continuous assignments */

/* Package instantiations */
CAPACITOR C2 ( 
    .\1  ( unnamed_net2 ),
    .\2  ( Vbase2 )
    );

RESISTOR R4 ( 
    .\2  ( Vbase2 ),
    .\1  ( GND )
    );

RESISTOR R3 ( 
    .\2  ( Vcc ),
    .\1  ( Vbase2 )
    );

RESISTOR R8 ( 
    .\2  ( unnamed_net2 ),
    .\1  ( Vcoll1 )
    );

CAPACITOR CE2 ( 
    .\1  ( GND ),
    .\2  ( Vem2 )
    );

RESISTOR RE2 ( 
    .\2  ( Vem2 ),
    .\1  ( GND )
    );

RESISTOR RC1 ( 
    .\2  ( Vcc ),
    .\1  ( Vcoll1 )
    );

NPN_TRANSISTOR Q2 ( 
    .\3  ( VColl2 ),
    .\1  ( Vem2 ),
    .\2  ( Vbase2 )
    );

CAPACITOR C1 ( 
    .\1  ( unnamed_net1 ),
    .\2  ( Vbase1 )
    );

directive A3 (     );

include A2 (     );

model A1 (     );

VOLTAGE_SOURCE VCC ( 
    .\1  ( Vcc ),
    .\2  ( GND )
    );

vsin Vinput ( 
    .\1  ( Vin ),
    .\2  ( GND )
    );

CAPACITOR CE1 ( 
    .\1  ( GND ),
    .\2  ( Vem1 )
    );

CAPACITOR Cout ( 
    .\1  ( VColl2 ),
    .\2  ( Vout )
    );

RESISTOR RL ( 
    .\2  ( Vout ),
    .\1  ( GND )
    );

RESISTOR RC2 ( 
    .\2  ( Vcc ),
    .\1  ( VColl2 )
    );

RESISTOR RE1 ( 
    .\2  ( Vem1 ),
    .\1  ( GND )
    );

RESISTOR R2 ( 
    .\2  ( Vbase1 ),
    .\1  ( GND )
    );

RESISTOR R1 ( 
    .\2  ( Vcc ),
    .\1  ( Vbase1 )
    );

RESISTOR R5 ( 
    .\2  ( unnamed_net1 ),
    .\1  ( Vin )
    );

NPN_TRANSISTOR Q1 ( 
    .\3  ( Vcoll1 ),
    .\1  ( Vem1 ),
    .\2  ( Vbase1 )
    );

endmodule