/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire GND ;
wire unnamed_net1 ;

/* continuous assignments */

/* Package instantiations */
VOLTAGE_SOURCE V1 ( 
    .\1  ( unnamed_net1 ),
    .\2  ( GND )
    );

RESISTOR R1 ( 
    .\2  ( unnamed_net1 ),
    .\1  ( GND )
    );

options A1 (     );

endmodule