/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire unnamed_net1 ;
wire netattrib ;
wire GND ;
wire Vcc ;
wire one ;

/* continuous assignments */

/* Package instantiations */
FUSE F1 ( 
    .\1  ( one )
    );

\7404  U300 ( 
    .\1  ( one ),
    .\2  ( unnamed_net1 ),
    .\7  ( GND ),
    .\14  ( Vcc )
    );

\7404  U200 ( 
    .\1  ( one ),
    .\2  ( netattrib ),
    .\7  ( GND ),
    .\14  ( Vcc )
    );

\7400  U100 ( 
    .\3  ( one ),
    .\14  ( Vcc ),
    .\7  ( GND ),
    .\5  ( netattrib )
    );

endmodule