/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire ten ;
wire eleven ;
wire GND ;
wire one ;
wire five ;
wire three ;
wire two ;
wire six ;
wire seven ;
wire nine ;
wire eight ;

/* continuous assignments */

/* Package instantiations */
LM317 U2 ( 
    .\2  ( eleven ),
    .\3  ( eight ),
    .\1  ( ten )
    );

POLARIZED_CAPACITOR C4 ( 
    .\1  ( eleven ),
    .\2  ( nine )
    );

POLARIZED_CAPACITOR C3 ( 
    .\1  ( ten ),
    .\2  ( nine )
    );

VARIABLE_RESISTOR R1 ( 
    .\3  ( nine ),
    .\2  ( ten ),
    .\1  ( nine )
    );

POLARIZED_CAPACITOR C2 ( 
    .\1  ( eight ),
    .\2  ( nine )
    );

RESISTOR R2 ( 
    .\2  ( eleven ),
    .\1  ( ten )
    );

POLARIZED_CAPACITOR C1 ( 
    .\1  ( eight ),
    .\2  ( nine )
    );

SPST S1 ( 
    .\2  ( two ),
    .\1  ( one )
    );

MAINS_CONNECTOR CONN1 ( 
    .\1  ( one ),
    .\2  ( five ),
    .\3  ( GND )
    );

transformer T1 ( 
    .\2  ( five ),
    .\1  ( three ),
    .\4  ( seven ),
    .\3  ( six )
    );

FUSE F1 ( 
    .\1  ( two ),
    .\2  ( three )
    );

\DIODE-BRIDGE  U1 ( 
    .\1  ( eight ),
    .\2  ( nine ),
    .\3  ( seven ),
    .\4  ( six )
    );

endmodule