/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/*        made here will be lost next time  */
/*        you run gnetlist!                 */
/* Id ..........$Id$ */
/* Source.......$Source$ */
/* Revision.....$Revision$ */
/* Author.......$Author$ */

module \not found  (

      );

/* Port directions begin here */


/* Wires from the design */
wire SING_N_2 ;
wire GND ;
wire Vcc ;
wire SING_N ;

/* continuous assignments */

/* Package instantiations */
\7400  U100 ( 
    .\6  ( SING_N ),
    .\5  ( SING_N ),
    .\4  ( SING_N ),
    .\14  ( Vcc ),
    .\7  ( GND ),
    .\3  ( SING_N_2 ),
    .\1  ( SING_N_2 ),
    .\14  ( Vcc ),
    .\7  ( GND ),
    .\8  ( SING_N ),
    .\10  ( SING_N ),
    .\9  ( SING_N ),
    .\14  ( Vcc ),
    .\7  ( GND )
    );

endmodule