-- Structural VHDL generated by gnetlist -- Context clause library IEEE; use IEEE.Std_Logic_1164.all; -- Entity declaration ENTITY not found IS END not found; -- Secondary unit ARCHITECTURE netlist OF not found IS COMPONENT LVD END COMPONENT ; COMPONENT PMOS_TRANSISTOR END COMPONENT ; COMPONENT RESISTOR END COMPONENT ; COMPONENT vpulse END COMPONENT ; COMPONENT VOLTAGE_SOURCE END COMPONENT ; COMPONENT CAPACITOR END COMPONENT ; COMPONENT model END COMPONENT ; SIGNAL Vdd1 : Std_Logic; SIGNAL GND : Std_Logic; SIGNAL LVH : Std_Logic; SIGNAL i : Std_Logic; SIGNAL p : Std_Logic; SIGNAL m : Std_Logic; BEGIN -- Architecture statement part A1 : model ; Cm : CAPACITOR PORT MAP ( 1 => m, 2 => GND); Cp : CAPACITOR PORT MAP ( 1 => p, 2 => GND); Rlp : RESISTOR PORT MAP ( 2 => Vdd1, 1 => p); Rlm : RESISTOR PORT MAP ( 2 => GND, 1 => m); Vdd : VOLTAGE_SOURCE PORT MAP ( 1 => Vdd1, 2 => GND); V1 : vpulse PORT MAP ( 1 => i, 2 => GND); Rt : RESISTOR PORT MAP ( 2 => m, 1 => p); Rb : RESISTOR PORT MAP ( 2 => LVH, 1 => GND); M1 : PMOS_TRANSISTOR PORT MAP ( S => Vdd1, B => Vdd1, D => LVH, G => LVH); X1 : LVD PORT MAP ( 4 => m, 5 => p, 1 => i, 3 => LVH, 2 => GND, 6 => Vdd1, 7 => GND); -- Signal assignment part END netlist;