-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT LM324
    END COMPONENT ;

    SIGNAL minusin_slot4_pin13_b : Std_Logic;
    SIGNAL plusin_slot4_pin12_a : Std_Logic;
    SIGNAL minusin_slot3_pin_b : Std_Logic;
    SIGNAL plusin_slot3_pin10_a : Std_Logic;
    SIGNAL minusin_slot2_pin6_b : Std_Logic;
    SIGNAL plusin_slot2_pin5_a : Std_Logic;
    SIGNAL samenet_output_c : Std_Logic;
    SIGNAL minusin_slot1_pin_b : Std_Logic;
    SIGNAL plusin_slot1_pin3_a : Std_Logic;
BEGIN
-- Architecture statement part
    U1 : LM324
    PORT MAP (
        3 => plusin_slot1_pin3_a,
        2 => minusin_slot1_pin_b,
        1 => samenet_output_c,
        5 => plusin_slot2_pin5_a,
        6 => minusin_slot2_pin6_b,
        7 => samenet_output_c,
        10 => plusin_slot3_pin10_a,
        9 => minusin_slot3_pin_b,
        8 => samenet_output_c,
        12 => plusin_slot4_pin12_a,
        13 => minusin_slot4_pin13_b,
        14 => samenet_output_c);

-- Signal assignment part
END netlist;