-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT NPN_TRANSISTOR
    END COMPONENT ;

    COMPONENT RESISTOR
    END COMPONENT ;

    COMPONENT CAPACITOR
    END COMPONENT ;

    COMPONENT vsin
    END COMPONENT ;

    COMPONENT VOLTAGE_SOURCE
    END COMPONENT ;

    COMPONENT model
    END COMPONENT ;

    COMPONENT include
    END COMPONENT ;

    COMPONENT directive
    END COMPONENT ;

    SIGNAL unnamed_net2 : Std_Logic;
    SIGNAL Vbase2 : Std_Logic;
    SIGNAL Vem2 : Std_Logic;
    SIGNAL Vout : Std_Logic;
    SIGNAL VColl2 : Std_Logic;
    SIGNAL GND : Std_Logic;
    SIGNAL Vcc : Std_Logic;
    SIGNAL Vin : Std_Logic;
    SIGNAL unnamed_net1 : Std_Logic;
    SIGNAL Vbase1 : Std_Logic;
    SIGNAL Vem1 : Std_Logic;
    SIGNAL Vcoll1 : Std_Logic;
BEGIN
-- Architecture statement part
    C2 : CAPACITOR
    PORT MAP (
        1 => unnamed_net2,
        2 => Vbase2);

    R4 : RESISTOR
    PORT MAP (
        2 => Vbase2,
        1 => GND);

    R3 : RESISTOR
    PORT MAP (
        2 => Vcc,
        1 => Vbase2);

    R8 : RESISTOR
    PORT MAP (
        2 => unnamed_net2,
        1 => Vcoll1);

    CE2 : CAPACITOR
    PORT MAP (
        1 => GND,
        2 => Vem2);

    RE2 : RESISTOR
    PORT MAP (
        2 => Vem2,
        1 => GND);

    RC1 : RESISTOR
    PORT MAP (
        2 => Vcc,
        1 => Vcoll1);

    Q2 : NPN_TRANSISTOR
    PORT MAP (
        3 => VColl2,
        1 => Vem2,
        2 => Vbase2);

    C1 : CAPACITOR
    PORT MAP (
        1 => unnamed_net1,
        2 => Vbase1);

    A3 : directive
;

    A2 : include
;

    A1 : model
;

    VCC : VOLTAGE_SOURCE
    PORT MAP (
        1 => Vcc,
        2 => GND);

    Vinput : vsin
    PORT MAP (
        1 => Vin,
        2 => GND);

    CE1 : CAPACITOR
    PORT MAP (
        1 => GND,
        2 => Vem1);

    Cout : CAPACITOR
    PORT MAP (
        1 => VColl2,
        2 => Vout);

    RL : RESISTOR
    PORT MAP (
        2 => Vout,
        1 => GND);

    RC2 : RESISTOR
    PORT MAP (
        2 => Vcc,
        1 => VColl2);

    RE1 : RESISTOR
    PORT MAP (
        2 => Vem1,
        1 => GND);

    R2 : RESISTOR
    PORT MAP (
        2 => Vbase1,
        1 => GND);

    R1 : RESISTOR
    PORT MAP (
        2 => Vcc,
        1 => Vbase1);

    R5 : RESISTOR
    PORT MAP (
        2 => unnamed_net1,
        1 => Vin);

    Q1 : NPN_TRANSISTOR
    PORT MAP (
        3 => Vcoll1,
        1 => Vem1,
        2 => Vbase1);

-- Signal assignment part
END netlist;