-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT cascade-defaults-top
    END COMPONENT ;

    COMPONENT cascade-source
    END COMPONENT ;

    COMPONENT cascade-amp
    END COMPONENT ;

    COMPONENT cascade-defaults
    END COMPONENT ;

    COMPONENT cascade-filter
    END COMPONENT ;

    COMPONENT cascade-mixer
    END COMPONENT ;

    COMPONENT cascade-transformer
    END COMPONENT ;

    SIGNAL unnamed_net6 : Std_Logic;
    SIGNAL unnamed_net5 : Std_Logic;
    SIGNAL unnamed_net4 : Std_Logic;
    SIGNAL unnamed_net3 : Std_Logic;
    SIGNAL unnamed_net2 : Std_Logic;
    SIGNAL unnamed_net1 : Std_Logic;
    SIGNAL GND : Std_Logic;
BEGIN
-- Architecture statement part
    AMP2 : cascade-amp
    PORT MAP (
        1 => unnamed_net6,
        2 => OPEN);

    T1 : cascade-transformer
    PORT MAP (
        1 => unnamed_net5,
        2 => unnamed_net6);

    MX1 : cascade-mixer
    PORT MAP (
        1 => unnamed_net4,
        2 => unnamed_net5);

    FL1 : cascade-filter
    PORT MAP (
        1 => unnamed_net3,
        2 => unnamed_net4);

    DEF1 : cascade-defaults
    PORT MAP (
        1 => unnamed_net2,
        2 => unnamed_net3);

    AMP1 : cascade-amp
    PORT MAP (
        1 => unnamed_net1,
        2 => unnamed_net2);

    SOURCE : cascade-source
    PORT MAP (
        1 => unnamed_net1);

    DEFAULTS : cascade-defaults-top
    PORT MAP (
        1 => GND);

-- Signal assignment part
END netlist;