-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT options
    END COMPONENT ;

    COMPONENT RESISTOR
    END COMPONENT ;

    COMPONENT VOLTAGE_SOURCE
    END COMPONENT ;

    SIGNAL GND : Std_Logic;
    SIGNAL unnamed_net1 : Std_Logic;
BEGIN
-- Architecture statement part
    V1 : VOLTAGE_SOURCE
    PORT MAP (
        1 => unnamed_net1,
        2 => GND);

    R1 : RESISTOR
    PORT MAP (
        2 => unnamed_net1,
        1 => GND);

    A1 : options
;

-- Signal assignment part
END netlist;