-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT 7400
    END COMPONENT ;

    COMPONENT 7404
    END COMPONENT ;

    COMPONENT FUSE
    END COMPONENT ;

    SIGNAL unnamed_net1 : Std_Logic;
    SIGNAL netattrib : Std_Logic;
    SIGNAL GND : Std_Logic;
    SIGNAL Vcc : Std_Logic;
    SIGNAL one : Std_Logic;
BEGIN
-- Architecture statement part
    F1 : FUSE
    PORT MAP (
        1 => one,
        2 => OPEN);

    U300 : 7404
    PORT MAP (
        1 => one,
        2 => unnamed_net1,
        7 => GND,
        14 => Vcc);

    U200 : 7404
    PORT MAP (
        1 => one,
        2 => netattrib,
        7 => GND,
        14 => Vcc);

    U100 : 7400
    PORT MAP (
        3 => one,
        2 => OPEN,
        1 => OPEN,
        14 => Vcc,
        7 => GND,
        5 => netattrib);

-- Signal assignment part
END netlist;