-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT DIODE-BRIDGE
    END COMPONENT ;

    COMPONENT FUSE
    END COMPONENT ;

    COMPONENT transformer
    END COMPONENT ;

    COMPONENT MAINS_CONNECTOR
    END COMPONENT ;

    COMPONENT SPST
    END COMPONENT ;

    COMPONENT POLARIZED_CAPACITOR
    END COMPONENT ;

    COMPONENT RESISTOR
    END COMPONENT ;

    COMPONENT VARIABLE_RESISTOR
    END COMPONENT ;

    COMPONENT LM317
    END COMPONENT ;

    SIGNAL ten : Std_Logic;
    SIGNAL eleven : Std_Logic;
    SIGNAL GND : Std_Logic;
    SIGNAL one : Std_Logic;
    SIGNAL five : Std_Logic;
    SIGNAL three : Std_Logic;
    SIGNAL two : Std_Logic;
    SIGNAL six : Std_Logic;
    SIGNAL seven : Std_Logic;
    SIGNAL nine : Std_Logic;
    SIGNAL eight : Std_Logic;
BEGIN
-- Architecture statement part
    U2 : LM317
    PORT MAP (
        2 => eleven,
        3 => eight,
        1 => ten);

    C4 : POLARIZED_CAPACITOR
    PORT MAP (
        1 => eleven,
        2 => nine);

    C3 : POLARIZED_CAPACITOR
    PORT MAP (
        1 => ten,
        2 => nine);

    R1 : VARIABLE_RESISTOR
    PORT MAP (
        3 => nine,
        2 => ten,
        1 => nine);

    C2 : POLARIZED_CAPACITOR
    PORT MAP (
        1 => eight,
        2 => nine);

    R2 : RESISTOR
    PORT MAP (
        2 => eleven,
        1 => ten);

    C1 : POLARIZED_CAPACITOR
    PORT MAP (
        1 => eight,
        2 => nine);

    S1 : SPST
    PORT MAP (
        2 => two,
        1 => one);

    CONN1 : MAINS_CONNECTOR
    PORT MAP (
        1 => one,
        2 => five,
        3 => GND);

    T1 : transformer
    PORT MAP (
        2 => five,
        1 => three,
        4 => seven,
        3 => six);

    F1 : FUSE
    PORT MAP (
        1 => two,
        2 => three);

    U1 : DIODE-BRIDGE
    PORT MAP (
        1 => eight,
        2 => nine,
        3 => seven,
        4 => six);

-- Signal assignment part
END netlist;