-- Structural VHDL generated by gnetlist
-- Context clause
library IEEE;
use IEEE.Std_Logic_1164.all;
-- Entity declaration

ENTITY not found IS
END not found;


-- Secondary unit
ARCHITECTURE netlist OF not found IS
    COMPONENT 7400
    END COMPONENT ;

    SIGNAL SING_N_2 : Std_Logic;
    SIGNAL GND : Std_Logic;
    SIGNAL Vcc : Std_Logic;
    SIGNAL SING_N : Std_Logic;
BEGIN
-- Architecture statement part
    U100 : 7400
    PORT MAP (
        6 => SING_N,
        5 => SING_N,
        4 => SING_N,
        14 => Vcc,
        7 => GND,
        3 => SING_N_2,
        2 => OPEN,
        1 => SING_N_2,
        14 => Vcc,
        7 => GND,
        8 => SING_N,
        10 => SING_N,
        9 => SING_N,
        14 => Vcc,
        7 => GND);

-- Signal assignment part
END netlist;