v 20030901
C 17400 25700 1 0 0 7400-1.sym
{
T 17700 26700 5 10 1 1 0 0
refdes=U100
T 17400 25700 5 10 0 0 0 0
slot=2
}
N 18700 26200 21300 26200 4
N 21300 26200 21300 24400 4
N 21300 24400 22600 24400 4
N 22600 24000 20300 24000 4
N 20300 24000 20300 26200 4
N 21300 25300 24100 25300 4
{
T 22700 25400 5 10 1 1 0 0
netname=SINGLE_NET
}
N 24100 25300 24100 24200 4
N 24100 24200 23900 24200 4
N 17400 26000 17000 26000 4
N 17000 26000 17000 25300 4
N 17000 25300 18800 25300 4
N 18800 25300 18800 26200 4
N 17400 26400 17200 26400 4
N 17200 26400 17200 27200 4
N 17200 27200 19800 27200 4
N 19800 27200 19800 26200 4
T 17900 35200 3 30 1 0 0 0
Test schematic for gnetlist
T 17100 27600 3 20 1 0 0 0
There is really only *one* net in this circuit
N 19000 33100 21800 33100 4
{
T 20400 33200 5 10 1 1 0 0
netname=SINGLE_NET2
}
N 21800 33100 21800 32000 4
N 21800 32000 21600 32000 4
N 19000 33100 19000 32200 4
N 19000 32200 20300 32200 4
T 17200 30200 3 20 1 0 0 0
This is a single net with one unconnected pin
C 20300 31500 1 0 0 7400-1.sym
{
T 20600 32500 5 10 1 1 0 0
refdes=U100
T 20300 31500 5 10 0 0 0 0
slot=1
}
C 22600 23700 1 0 0 7400-1.sym
{
T 22900 24700 5 10 1 1 0 0
refdes=U100
T 22600 23700 5 10 0 0 0 0
slot=3
}