(Allegro netlister by M. Ettus)
$PACKAGES
! model! model; A1
! CAPACITOR! 20p; Cm
! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
! RESISTOR! 500k; Rlm
none! VOLTAGE_SOURCE! DC 3.3V; Vdd
none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
 M1.B,
 M1.S,
 Vdd.1,
 X1.6
GND; Cm.2,
 Cp.2,
 Rlm.2,
 Vdd.2,
 V1.2,
 Rb.1,
 X1.7,
 X1.2
LVH; Rb.2,
 M1.D,
 M1.G,
 X1.3
i; V1.1,
 X1.1
p; Cp.1,
 Rt.1,
 Rlp.1,
 X1.5
m; Cm.1,
 Rlm.1,
 Rt.2,
 X1.4
$END