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<div class="document" id="uhd-usrp1-device-manual">
<h1 class="title">UHD - USRP1 Device Manual</h1>
<div class="contents topic" id="table-of-contents">
<p class="topic-title first">Table of Contents</p>
<ul class="simple">
<li><a class="reference internal" href="#comparative-features-list" id="id1">Comparative features list</a></li>
<li><a class="reference internal" href="#specify-a-non-standard-image" id="id2">Specify a Non-standard Image</a></li>
<li><a class="reference internal" href="#missing-and-emulated-features" id="id3">Missing and Emulated Features</a><ul>
<li><a class="reference internal" href="#list-of-emulated-features" id="id4">List of emulated features</a></li>
<li><a class="reference internal" href="#list-of-missing-features" id="id5">List of missing features</a></li>
</ul>
</li>
<li><a class="reference internal" href="#hardware-setup-notes" id="id6">Hardware Setup Notes</a><ul>
<li><a class="reference internal" href="#external-clock-modification" id="id7">External clock modification</a></li>
</ul>
</li>
</ul>
</div>
<div class="section" id="comparative-features-list">
<h1>Comparative features list</h1>
<dl class="docutils">
<dt><strong>Hardware Capabilities:</strong></dt>
<dd><ul class="first last simple">
<li>2 transceiver card slots</li>
<li>64 MHz fixed clock rate</li>
</ul>
</dd>
<dt><strong>FPGA Capabilities:</strong></dt>
<dd><ul class="first last simple">
<li>2 RX DDC chains in FPGA</li>
<li>2 TX DUC chains in FPGA (no TX CORDIC -> uses DAC)</li>
<li>sc16 sample modes - RX & TX<ul>
<li>Up to 8 MHz of RF BW with 16-bit samples</li>
</ul>
</li>
<li>sc8 sample mode - RX only<ul>
<li>Up to 16 MHz of RF BW with 8-bit samples</li>
</ul>
</li>
</ul>
</dd>
</dl>
</div>
<div class="section" id="specify-a-non-standard-image">
<h1>Specify a Non-standard Image</h1>
<dl class="docutils">
<dt>The standard USRP1 images installer comes with two FPGA images:</dt>
<dd><ul class="first last simple">
<li><strong>usrp1_fpga.rbf:</strong> 2 DDCs + 2 DUCs</li>
<li><strong>usrp1_fpga_4rx.rbf:</strong> 4 DDCs + 0 DUCs</li>
</ul>
</dd>
</dl>
<p>By default, the USRP1 uses the FPGA image with 2 DDCs and 2 DUCs.
However, a device address parameter can be used to override
the FPGA image selection to use an alternate or a custom FPGA image.
See the images application notes for installing custom images.</p>
<p>Example device address string representations to specify non-standard firmware and/or FPGA images:</p>
<pre class="literal-block">
fpga=usrp1_fpga_4rx.rbf
-- OR --
fw=usrp1_fw_custom.ihx
-- OR --
fpga=usrp1_fpga_4rx.rbf, fw=usrp1_fw_custom.ihx
</pre>
</div>
<div class="section" id="missing-and-emulated-features">
<h1>Missing and Emulated Features</h1>
<p>The USRP1 FPGA does not have the necessary space to support the advanced
streaming capabilities that are possible with the newer USRP devices.
Some of these features are emulated in software to support the API.</p>
<div class="section" id="list-of-emulated-features">
<h2>List of emulated features</h2>
<ul class="simple">
<li>Setting the current device time</li>
<li>Getting the current device time</li>
<li>Transmitting at a specific time</li>
<li>Transmitting a specific number of samples</li>
<li>Receiving at a specific time</li>
<li>Receiving a specific number of samples</li>
<li>End of burst flags for transmit/receive</li>
<li>Notification on late stream command</li>
<li>Notification on late transmit packet</li>
<li>Notification on underflow or overflow</li>
<li>Notification on broken chain error</li>
</ul>
<p><strong>Note:</strong>
These emulated features rely on the host system's clock for timed operations
and therefore may not have sufficient precision for the application.</p>
</div>
<div class="section" id="list-of-missing-features">
<h2>List of missing features</h2>
<ul class="simple">
<li>Start of burst flags for transmit/receive</li>
</ul>
</div>
</div>
<div class="section" id="hardware-setup-notes">
<h1>Hardware Setup Notes</h1>
<div class="section" id="external-clock-modification">
<h2>External clock modification</h2>
<dl class="docutils">
<dt>The USRP device can be modified to accept an external clock reference instead of the 64MHz onboard reference.</dt>
<dd><ul class="first last simple">
<li>Solder SMA (<strong>LTI-SASF54GT</strong>) connector to <strong>J2001</strong>.</li>
<li>Move 0 ohm 0603 resistor <strong>R2029</strong> to <strong>R2030</strong>.</li>
<li>Move 0.01uF 0603 capacitor <strong>C925</strong> to <strong>C926</strong>.</li>
<li>Remove 0.01uF 0603 capacitor <strong>C924</strong>.</li>
</ul>
</dd>
</dl>
<p>The new external clock needs to be a square wave between +7dBm and +15dBm</p>
<p>After the hardware modification,
the user should burn the setting into the EEPROM,
so UHD software can initialize with the correct clock rate.
Run the following commands to record the setting into the EEPROM:</p>
<pre class="literal-block">
cd <install-path>/lib/uhd/utils
./usrp_burn_mb_eeprom --args=<optional device args> --key=mcr --val=<rate>
</pre>
<p>The user may override the clock rate specified in the EEPROM by using a device address:
Example:</p>
<pre class="literal-block">
uhd_usrp_probe --args="mcr=52e6"
</pre>
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