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<div class="document" id="uhd-usrp-b100-series-device-manual">
<h1 class="title">UHD - USRP-B100 Series Device Manual</h1>
<div class="contents topic" id="table-of-contents">
<p class="topic-title first">Table of Contents</p>
<ul class="simple">
<li><a class="reference internal" href="#comparative-features-list" id="id1">Comparative features list</a></li>
<li><a class="reference internal" href="#specify-a-non-standard-image" id="id2">Specify a Non-standard Image</a></li>
<li><a class="reference internal" href="#changing-the-master-clock-rate" id="id3">Changing the Master Clock Rate</a><ul>
<li><a class="reference internal" href="#set-61-44-mhz-uses-external-vcxo" id="id4">Set 61.44 MHz - uses external VCXO</a></li>
<li><a class="reference internal" href="#set-other-rates-uses-internal-vco" id="id5">Set other rates - uses internal VCO</a></li>
</ul>
</li>
<li><a class="reference internal" href="#hardware-setup-notes" id="id6">Hardware setup notes</a><ul>
<li><a class="reference internal" href="#front-panel-leds" id="id7">Front panel LEDs</a></li>
</ul>
</li>
<li><a class="reference internal" href="#miscellaneous" id="id8">Miscellaneous</a><ul>
<li><a class="reference internal" href="#available-sensors" id="id9">Available Sensors</a></li>
</ul>
</li>
</ul>
</div>
<div class="section" id="comparative-features-list">
<h1>Comparative features list</h1>
<dl class="docutils">
<dt><strong>Hardware Capabilities:</strong></dt>
<dd><ul class="first last simple">
<li>1 transceiver card slot</li>
<li>External PPS reference input</li>
<li>External 10 MHz reference input</li>
<li>Configurable clock rate (defaults 64 MHz)</li>
</ul>
</dd>
<dt><strong>FPGA Capabilities:</strong></dt>
<dd><ul class="first last simple">
<li>1 RX DDC chain in FPGA</li>
<li>1 TX DUC chain in FPGA</li>
<li>Timed commands in FPGA</li>
<li>Timed sampling in FPGA</li>
<li>sc8 and sc16 sample modes<ul>
<li>Up to 8 MHz of RF BW with 16-bit samples</li>
<li>Up to 16 MHz of RF BW with 8-bit samples</li>
</ul>
</li>
</ul>
</dd>
</dl>
</div>
<div class="section" id="specify-a-non-standard-image">
<h1>Specify a Non-standard Image</h1>
<p>UHD software will automatically select the USRP B100 images from the installed images package.
The image selection can be overridden with the <strong>--fpga=</strong> and <strong>--fw=</strong> device address parameters.</p>
<p>Example device address string representations to specify non-standard images:</p>
<pre class="literal-block">
fpga=usrp_b100_fpga_2rx.bin
-- OR --
fw=usrp_b100_fw.ihx
</pre>
</div>
<div class="section" id="changing-the-master-clock-rate">
<h1>Changing the Master Clock Rate</h1>
<p>The master clock rate of the B100 feeds both the FPGA DSP and the codec chip.
Hundreds of rates between 32 MHz and 64 MHz are available.
A few notable rates are:</p>
<ul class="simple">
<li><strong>64 MHz:</strong> maximum rate of the codec chip</li>
<li><strong>61.44 MHz:</strong> good for UMTS/WCDMA applications</li>
<li><strong>52 MHz:</strong> good for GSM applications</li>
</ul>
<div class="section" id="set-61-44-mhz-uses-external-vcxo">
<h2>Set 61.44 MHz - uses external VCXO</h2>
<p>To use the 61.44 MHz clock rate, the USRP embedded will require one jumper to be moved,
and X4 must be populated with a 61.44 MHz oscillator.</p>
<ul class="simple">
<li><strong>J15</strong> is a three pin header, move the jumper to (pin1, pin2)</li>
<li><strong>357LB3I061M4400</strong> is the recommended oscillator for X4</li>
</ul>
<p><strong>Note:</strong> See instructions below to communicate the desired clock rate into UHD software.</p>
</div>
<div class="section" id="set-other-rates-uses-internal-vco">
<h2>Set other rates - uses internal VCO</h2>
<p>To use other clock rates, the jumper will need to be in the default position.</p>
<ul class="simple">
<li><strong>J15</strong> is a three pin header, move the jumper to (pin2, pin3)</li>
</ul>
<p>To communicate the desired clock rate into UHD software,
specify the special device address argument,
where the key is <strong>master_clock_rate</strong> and the value is a rate in Hz.
Example:</p>
<pre class="literal-block">
uhd_usrp_probe --args="master_clock_rate=52e6"
</pre>
</div>
</div>
<div class="section" id="hardware-setup-notes">
<h1>Hardware setup notes</h1>
<div class="section" id="front-panel-leds">
<h2>Front panel LEDs</h2>
<p>The LEDs on the front panel can be useful in debugging hardware and software issues.
The LEDs reveal the following about the state of the device:</p>
<ul class="simple">
<li><strong>LED A:</strong> transmitting</li>
<li><strong>LED B:</strong> FPGA loaded</li>
<li><strong>LED C:</strong> receiving</li>
<li><strong>LED D:</strong> FPGA loaded</li>
<li><strong>LED E:</strong> reference lock</li>
<li><strong>LED F:</strong> board power</li>
</ul>
</div>
</div>
<div class="section" id="miscellaneous">
<h1>Miscellaneous</h1>
<div class="section" id="available-sensors">
<h2>Available Sensors</h2>
<p>The following sensors are available;
they can be queried through the API.</p>
<ul class="simple">
<li><strong>ref_locked:</strong> clock reference locked (internal/external)</li>
</ul>
</div>
</div>
</div>
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Generated on: 2014-10-15 11:47 UTC.
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