* Interrupt Controller

Properties:
- compatible: "brcm,bcm3384-intc"

  Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.

- reg: Address/length pairs for each mask/status register set.  Length must
  be 8.  If multiple register sets are specified, the first set will
  handle IRQ offsets 0..31, the second set 32..63, and so on.

- interrupt-controller: This is an interrupt controller.

- #interrupt-cells: Must be <1>.  Just a simple IRQ offset; no level/edge
  or polarity configuration is possible with this controller.

- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or
  from another INTC.

- interrupts: The IRQ on the parent controller.

Example:
	periph_intc: periph_intc@14e00038 {
		compatible = "brcm,bcm3384-intc";

		/*
		 * IRQs 0..31:  mask reg 0x14e00038, status reg 0x14e0003c
		 * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344
		 */
		reg = <0x14e00038 0x8 0x14e00340 0x8>;

		interrupt-controller;
		#interrupt-cells = <1>;

		interrupt-parent = <&cpu_intc>;
		interrupts = <4>;
	};