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<div class="title">Acceleration flags</div> </div>
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<p>CPU specific acceleration flags.
<a href="#details">More...</a></p>
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Macros</h2></td></tr>
<tr class="memitem:ga396b945ed3895dbf9c7e086c9769511b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga396b945ed3895dbf9c7e086c9769511b">GAVL_ACCEL_MMX</a>   (1<<0)</td></tr>
<tr class="memdesc:ga396b945ed3895dbf9c7e086c9769511b"><td class="mdescLeft"> </td><td class="mdescRight">MMX. <a href="#ga396b945ed3895dbf9c7e086c9769511b">More...</a><br /></td></tr>
<tr class="separator:ga396b945ed3895dbf9c7e086c9769511b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga6ff656ed250442d5e7ab15faaf8de449"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga6ff656ed250442d5e7ab15faaf8de449">GAVL_ACCEL_MMXEXT</a>   (1<<1)</td></tr>
<tr class="memdesc:ga6ff656ed250442d5e7ab15faaf8de449"><td class="mdescLeft"> </td><td class="mdescRight">Extended MMX (a.k.a MMX2) <a href="#ga6ff656ed250442d5e7ab15faaf8de449">More...</a><br /></td></tr>
<tr class="separator:ga6ff656ed250442d5e7ab15faaf8de449"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8d2cb2b3327e4626d1a22f9b98e065ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga8d2cb2b3327e4626d1a22f9b98e065ba">GAVL_ACCEL_SSE</a>   (1<<2)</td></tr>
<tr class="memdesc:ga8d2cb2b3327e4626d1a22f9b98e065ba"><td class="mdescLeft"> </td><td class="mdescRight">Intel SSE. <a href="#ga8d2cb2b3327e4626d1a22f9b98e065ba">More...</a><br /></td></tr>
<tr class="separator:ga8d2cb2b3327e4626d1a22f9b98e065ba"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga2ad2bb06c442d970febd989d5e9c434f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga2ad2bb06c442d970febd989d5e9c434f">GAVL_ACCEL_SSE2</a>   (1<<3)</td></tr>
<tr class="memdesc:ga2ad2bb06c442d970febd989d5e9c434f"><td class="mdescLeft"> </td><td class="mdescRight">Intel SSE2. <a href="#ga2ad2bb06c442d970febd989d5e9c434f">More...</a><br /></td></tr>
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<tr class="memitem:ga1c811566a7a5b8611807782bf6f56fc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga1c811566a7a5b8611807782bf6f56fc5">GAVL_ACCEL_SSE3</a>   (1<<4)</td></tr>
<tr class="memdesc:ga1c811566a7a5b8611807782bf6f56fc5"><td class="mdescLeft"> </td><td class="mdescRight">Intel SSE3. <a href="#ga1c811566a7a5b8611807782bf6f56fc5">More...</a><br /></td></tr>
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<tr class="memitem:ga1252e9a9b3b94299207643551e4e3a90"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga1252e9a9b3b94299207643551e4e3a90">GAVL_ACCEL_3DNOW</a>   (1<<5)</td></tr>
<tr class="memdesc:ga1252e9a9b3b94299207643551e4e3a90"><td class="mdescLeft"> </td><td class="mdescRight">AMD 3Dnow. <a href="#ga1252e9a9b3b94299207643551e4e3a90">More...</a><br /></td></tr>
<tr class="separator:ga1252e9a9b3b94299207643551e4e3a90"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga10bf859545e33246acb2321c0e6d1eda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga10bf859545e33246acb2321c0e6d1eda">GAVL_ACCEL_3DNOWEXT</a>   (1<<6)</td></tr>
<tr class="memdesc:ga10bf859545e33246acb2321c0e6d1eda"><td class="mdescLeft"> </td><td class="mdescRight">AMD 3Dnow ext. <a href="#ga10bf859545e33246acb2321c0e6d1eda">More...</a><br /></td></tr>
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<tr class="memitem:ga035e482e38fefb4e88a068698f5a4bbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga035e482e38fefb4e88a068698f5a4bbf">GAVL_ACCEL_SSSE3</a>   (1<<7)</td></tr>
<tr class="memdesc:ga035e482e38fefb4e88a068698f5a4bbf"><td class="mdescLeft"> </td><td class="mdescRight">Intel SSSE3. <a href="#ga035e482e38fefb4e88a068698f5a4bbf">More...</a><br /></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga9ee7b6f97f38d7f77a03f8e3b8fc47f3"><td class="memItemLeft" align="right" valign="top">GAVL_PUBLIC int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__accel__flags.html#ga9ee7b6f97f38d7f77a03f8e3b8fc47f3">gavl_accel_supported</a> ()</td></tr>
<tr class="memdesc:ga9ee7b6f97f38d7f77a03f8e3b8fc47f3"><td class="mdescLeft"> </td><td class="mdescRight">Get the supported acceleration flags. <a href="#ga9ee7b6f97f38d7f77a03f8e3b8fc47f3">More...</a><br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<p>CPU specific acceleration flags. </p>
<p>These flags are used internally by gavl to obtain the supported acceleration mechanisms at runtime. Some applications however might need them as well for other tasks, so they are exported into the public API. </p>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga396b945ed3895dbf9c7e086c9769511b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga396b945ed3895dbf9c7e086c9769511b">§ </a></span>GAVL_ACCEL_MMX</h2>
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<td class="memname">#define GAVL_ACCEL_MMX   (1<<0)</td>
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<p>MMX. </p>
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<a id="ga6ff656ed250442d5e7ab15faaf8de449"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6ff656ed250442d5e7ab15faaf8de449">§ </a></span>GAVL_ACCEL_MMXEXT</h2>
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<td class="memname">#define GAVL_ACCEL_MMXEXT   (1<<1)</td>
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<p>Extended MMX (a.k.a MMX2) </p>
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<a id="ga8d2cb2b3327e4626d1a22f9b98e065ba"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8d2cb2b3327e4626d1a22f9b98e065ba">§ </a></span>GAVL_ACCEL_SSE</h2>
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<td class="memname">#define GAVL_ACCEL_SSE   (1<<2)</td>
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<p>Intel SSE. </p>
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<a id="ga2ad2bb06c442d970febd989d5e9c434f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga2ad2bb06c442d970febd989d5e9c434f">§ </a></span>GAVL_ACCEL_SSE2</h2>
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<td class="memname">#define GAVL_ACCEL_SSE2   (1<<3)</td>
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<p>Intel SSE2. </p>
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<a id="ga1c811566a7a5b8611807782bf6f56fc5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1c811566a7a5b8611807782bf6f56fc5">§ </a></span>GAVL_ACCEL_SSE3</h2>
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<td class="memname">#define GAVL_ACCEL_SSE3   (1<<4)</td>
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<p>Intel SSE3. </p>
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<a id="ga1252e9a9b3b94299207643551e4e3a90"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1252e9a9b3b94299207643551e4e3a90">§ </a></span>GAVL_ACCEL_3DNOW</h2>
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<td class="memname">#define GAVL_ACCEL_3DNOW   (1<<5)</td>
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<p>AMD 3Dnow. </p>
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<a id="ga10bf859545e33246acb2321c0e6d1eda"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga10bf859545e33246acb2321c0e6d1eda">§ </a></span>GAVL_ACCEL_3DNOWEXT</h2>
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<td class="memname">#define GAVL_ACCEL_3DNOWEXT   (1<<6)</td>
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<p>AMD 3Dnow ext. </p>
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<a id="ga035e482e38fefb4e88a068698f5a4bbf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga035e482e38fefb4e88a068698f5a4bbf">§ </a></span>GAVL_ACCEL_SSSE3</h2>
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<td class="memname">#define GAVL_ACCEL_SSSE3   (1<<7)</td>
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<p>Intel SSSE3. </p>
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<h2 class="groupheader">Function Documentation</h2>
<a id="ga9ee7b6f97f38d7f77a03f8e3b8fc47f3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga9ee7b6f97f38d7f77a03f8e3b8fc47f3">§ </a></span>gavl_accel_supported()</h2>
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<td class="memname">GAVL_PUBLIC int gavl_accel_supported </td>
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<p>Get the supported acceleration flags. </p>
<dl class="section return"><dt>Returns</dt><dd>A combination of GAVL_ACCEL_* flags. </dd></dl>
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