# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CPM Host Controller device tree for Xilinx Versal SoCs

maintainers:
  - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    const: xlnx,versal-cpm-host-1.00

  reg:
    items:
      - description: Configuration space region and bridge registers.
      - description: CPM system level control and status registers.

  reg-names:
    items:
      - const: cfg
      - const: cpm_slcr

  interrupts:
    maxItems: 1

  msi-map:
    description:
      Maps a Requester ID to an MSI controller and associated MSI sideband data.

  ranges:
    maxItems: 2

  "#interrupt-cells":
    const: 1

  interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object
    properties:
      "#address-cells":
        const: 0
      "#interrupt-cells":
        const: 1
      "interrupt-controller": true
    additionalProperties: false

required:
  - reg
  - reg-names
  - "#interrupt-cells"
  - interrupts
  - interrupt-parent
  - interrupt-map
  - interrupt-map-mask
  - bus-range
  - msi-map
  - interrupt-controller

unevaluatedProperties: false

examples:
  - |

    versal {
               #address-cells = <2>;
               #size-cells = <2>;
               cpm_pcie: pcie@fca10000 {
                       compatible = "xlnx,versal-cpm-host-1.00";
                       device_type = "pci";
                       #address-cells = <3>;
                       #interrupt-cells = <1>;
                       #size-cells = <2>;
                       interrupts = <0 72 4>;
                       interrupt-parent = <&gic>;
                       interrupt-map-mask = <0 0 0 7>;
                       interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
                                       <0 0 0 2 &pcie_intc_0 1>,
                                       <0 0 0 3 &pcie_intc_0 2>,
                                       <0 0 0 4 &pcie_intc_0 3>;
                       bus-range = <0x00 0xff>;
                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
                       msi-map = <0x0 &its_gic 0x0 0x10000>;
                       reg = <0x6 0x00000000 0x0 0x10000000>,
                             <0x0 0xfca10000 0x0 0x1000>;
                       reg-names = "cfg", "cpm_slcr";
                       pcie_intc_0: interrupt-controller {
                               #address-cells = <0>;
                               #interrupt-cells = <1>;
                               interrupt-controller;
                       };
               };
    };