initSidebarItems({"fn":[["__breakpoint","Inserts a breakpoint instruction."],["__clrex","Removes the exclusive lock created by LDREX"],["__clrex","Removes the exclusive lock created by LDREX"],["__crc32b","CRC32 single round checksum for bytes (8 bits)."],["__crc32cb","CRC32-C single round checksum for bytes (8 bits)."],["__crc32cd","CRC32-C single round checksum for quad words (64 bits)."],["__crc32ch","CRC32-C single round checksum for half words (16 bits)."],["__crc32cw","CRC32-C single round checksum for words (32 bits)."],["__crc32d","CRC32 single round checksum for quad words (64 bits)."],["__crc32h","CRC32 single round checksum for half words (16 bits)."],["__crc32w","CRC32 single round checksum for words (32 bits)."],["__dbg","Generates a DBG instruction."],["__dbg","Generates a DBG instruction."],["__dmb","Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction."],["__dmb","Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction."],["__dsb","Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction."],["__dsb","Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction."],["__isb","Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction."],["__isb","Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction."],["__ldrex","Executes a exclusive LDR instruction for 32 bit value."],["__ldrex","Executes a exclusive LDR instruction for 32 bit value."],["__ldrexb","Executes a exclusive LDR instruction for 8 bit value."],["__ldrexb","Executes a exclusive LDR instruction for 8 bit value."],["__ldrexh","Executes a exclusive LDR instruction for 16 bit value."],["__ldrexh","Executes a exclusive LDR instruction for 16 bit value."],["__nop","Generates an unspecified no-op instruction."],["__nop","Generates an unspecified no-op instruction."],["__qadd","Signed saturating addition"],["__qadd","Signed saturating addition"],["__qadd16","Saturating two 16-bit integer additions"],["__qadd16","Saturating two 16-bit integer additions"],["__qadd8","Saturating four 8-bit integer additions"],["__qadd8","Saturating four 8-bit integer additions"],["__qasx","Returns the 16-bit signed saturated equivalent of"],["__qasx","Returns the 16-bit signed saturated equivalent of"],["__qdbl","Insert a QADD instruction"],["__qdbl","Insert a QADD instruction"],["__qsax","Returns the 16-bit signed saturated equivalent of"],["__qsax","Returns the 16-bit signed saturated equivalent of"],["__qsub","Signed saturating subtraction"],["__qsub","Signed saturating subtraction"],["__qsub16","Saturating two 16-bit integer subtraction"],["__qsub16","Saturating two 16-bit integer subtraction"],["__qsub8","Saturating two 8-bit integer subtraction"],["__qsub8","Saturating two 8-bit integer subtraction"],["__rsr","Reads a 32-bit system register"],["__rsr","Reads a 32-bit system register"],["__rsrp","Reads a system register containing an address"],["__rsrp","Reads a system register containing an address"],["__sadd16","Returns the 16-bit signed saturated equivalent of"],["__sadd16","Returns the 16-bit signed saturated equivalent of"],["__sadd8","Returns the 8-bit signed saturated equivalent of"],["__sadd8","Returns the 8-bit signed saturated equivalent of"],["__sasx","Returns the 16-bit signed equivalent of"],["__sasx","Returns the 16-bit signed equivalent of"],["__sel","Select bytes from each operand according to APSR GE flags"],["__sel","Select bytes from each operand according to APSR GE flags"],["__sev","Generates a SEV (send a global event) hint instruction."],["__sev","Generates a SEV (send a global event) hint instruction."],["__shadd16","Signed halving parallel halfword-wise addition."],["__shadd16","Signed halving parallel halfword-wise addition."],["__shadd8","Signed halving parallel byte-wise addition."],["__shadd8","Signed halving parallel byte-wise addition."],["__shsub16","Signed halving parallel halfword-wise subtraction."],["__shsub16","Signed halving parallel halfword-wise subtraction."],["__shsub8","Signed halving parallel byte-wise subtraction."],["__shsub8","Signed halving parallel byte-wise subtraction."],["__smlabb","Insert a SMLABB instruction"],["__smlabb","Insert a SMLABB instruction"],["__smlabt","Insert a SMLABT instruction"],["__smlabt","Insert a SMLABT instruction"],["__smlad","Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation."],["__smlad","Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation."],["__smlatb","Insert a SMLATB instruction"],["__smlatb","Insert a SMLATB instruction"],["__smlatt","Insert a SMLATT instruction"],["__smlatt","Insert a SMLATT instruction"],["__smlawb","Insert a SMLAWB instruction"],["__smlawb","Insert a SMLAWB instruction"],["__smlawt","Insert a SMLAWT instruction"],["__smlawt","Insert a SMLAWT instruction"],["__smlsd","Dual 16-bit Signed Multiply with Subtraction  of products and 32-bit accumulation and overflow detection."],["__smlsd","Dual 16-bit Signed Multiply with Subtraction  of products and 32-bit accumulation and overflow detection."],["__smuad","Signed Dual Multiply Add."],["__smuad","Signed Dual Multiply Add."],["__smuadx","Signed Dual Multiply Add Reversed."],["__smuadx","Signed Dual Multiply Add Reversed."],["__smulbb","Insert a SMULBB instruction"],["__smulbb","Insert a SMULBB instruction"],["__smulbt","Insert a SMULTB instruction"],["__smulbt","Insert a SMULTB instruction"],["__smultb","Insert a SMULTB instruction"],["__smultb","Insert a SMULTB instruction"],["__smultt","Insert a SMULTT instruction"],["__smultt","Insert a SMULTT instruction"],["__smulwb","Insert a SMULWB instruction"],["__smulwb","Insert a SMULWB instruction"],["__smulwt","Insert a SMULWT instruction"],["__smulwt","Insert a SMULWT instruction"],["__smusd","Signed Dual Multiply Subtract."],["__smusd","Signed Dual Multiply Subtract."],["__smusdx","Signed Dual Multiply Subtract Reversed."],["__smusdx","Signed Dual Multiply Subtract Reversed."],["__ssub8","Inserts a `SSUB8` instruction."],["__ssub8","Inserts a `SSUB8` instruction."],["__strex","Executes a exclusive STR instruction for 32 bit values"],["__strex","Executes a exclusive STR instruction for 32 bit values"],["__strexb","Executes a exclusive STR instruction for 8 bit values"],["__strexb","Executes a exclusive STR instruction for 8 bit values"],["__strexh","Executes a exclusive STR instruction for 16 bit values"],["__strexh","Executes a exclusive STR instruction for 16 bit values"],["__usad8","Sum of 8-bit absolute differences."],["__usad8","Sum of 8-bit absolute differences."],["__usada8","Sum of 8-bit absolute differences and constant."],["__usada8","Sum of 8-bit absolute differences and constant."],["__usub8","Inserts a `USUB8` instruction."],["__usub8","Inserts a `USUB8` instruction."],["__wfe","Generates a WFE (wait for event) hint instruction, or nothing."],["__wfe","Generates a WFE (wait for event) hint instruction, or nothing."],["__wfi","Generates a WFI (wait for interrupt) hint instruction, or nothing."],["__wfi","Generates a WFI (wait for interrupt) hint instruction, or nothing."],["__wsr","Writes a 32-bit system register"],["__wsr","Writes a 32-bit system register"],["__wsrp","Writes a system register containing an address"],["__wsrp","Writes a system register containing an address"],["__yield","Generates a YIELD hint instruction."],["__yield","Generates a YIELD hint instruction."],["_cls_u32","Counts the leading most significant bits set."],["_cls_u64","Counts the leading most significant bits set."],["_clz_u16","Count Leading Zeros."],["_clz_u32","Count Leading Zeros."],["_clz_u64","Count Leading Zeros."],["_clz_u8","Count Leading Zeros."],["_rbit_u32","Reverse the bit order."],["_rbit_u64","Reverse the bit order."],["_rev_u16","Reverse the order of the bytes."],["_rev_u16","Reverse the order of the bytes."],["_rev_u32","Reverse the order of the bytes."],["_rev_u32","Reverse the order of the bytes."],["_rev_u64","Reverse the order of the bytes."],["brk","Generates the trap instruction `BRK 1`"],["udf","Generates the trap instruction `UDF`"],["vadd_f32","Vector add."],["vadd_f64","Vector add."],["vadd_s16","Vector add."],["vadd_s32","Vector add."],["vadd_s8","Vector add."],["vadd_u16","Vector add."],["vadd_u32","Vector add."],["vadd_u8","Vector add."],["vaddd_s64","Vector add."],["vaddd_u64","Vector add."],["vaddl_s16","Vector long add."],["vaddl_s32","Vector long add."],["vaddl_s8","Vector long add."],["vaddl_u16","Vector long add."],["vaddl_u32","Vector long add."],["vaddl_u8","Vector long add."],["vaddq_f32","Vector add."],["vaddq_f64","Vector add."],["vaddq_s16","Vector add."],["vaddq_s32","Vector add."],["vaddq_s64","Vector add."],["vaddq_s8","Vector add."],["vaddq_u16","Vector add."],["vaddq_u32","Vector add."],["vaddq_u64","Vector add."],["vaddq_u8","Vector add."],["vaesdq_u8","AES single round decryption."],["vaeseq_u8","AES single round encryption."],["vaesimcq_u8","AES inverse mix columns."],["vaesmcq_u8","AES mix columns."],["vcombine_f32","Vector combine"],["vcombine_f64","Vector combine"],["vcombine_p16","Vector combine"],["vcombine_p64","Vector combine"],["vcombine_p8","Vector combine"],["vcombine_s16","Vector combine"],["vcombine_s32","Vector combine"],["vcombine_s64","Vector combine"],["vcombine_s8","Vector combine"],["vcombine_u16","Vector combine"],["vcombine_u32","Vector combine"],["vcombine_u64","Vector combine"],["vcombine_u8","Vector combine"],["vmaxv_f32","Horizontal vector max."],["vmaxv_s16","Horizontal vector max."],["vmaxv_s32","Horizontal vector max."],["vmaxv_s8","Horizontal vector max."],["vmaxv_u16","Horizontal vector max."],["vmaxv_u32","Horizontal vector max."],["vmaxv_u8","Horizontal vector max."],["vmaxvq_f32","Horizontal vector max."],["vmaxvq_f64","Horizontal vector max."],["vmaxvq_s16","Horizontal vector max."],["vmaxvq_s32","Horizontal vector max."],["vmaxvq_s8","Horizontal vector max."],["vmaxvq_u16","Horizontal vector max."],["vmaxvq_u32","Horizontal vector max."],["vmaxvq_u8","Horizontal vector max."],["vminv_f32","Horizontal vector min."],["vminv_s16","Horizontal vector min."],["vminv_s32","Horizontal vector min."],["vminv_s8","Horizontal vector min."],["vminv_u16","Horizontal vector min."],["vminv_u32","Horizontal vector min."],["vminv_u8","Horizontal vector min."],["vminvq_f32","Horizontal vector min."],["vminvq_f64","Horizontal vector min."],["vminvq_s16","Horizontal vector min."],["vminvq_s32","Horizontal vector min."],["vminvq_s8","Horizontal vector min."],["vminvq_u16","Horizontal vector min."],["vminvq_u32","Horizontal vector min."],["vminvq_u8","Horizontal vector min."],["vmovl_s16","Vector long move."],["vmovl_s32","Vector long move."],["vmovl_s8","Vector long move."],["vmovl_u16","Vector long move."],["vmovl_u32","Vector long move."],["vmovl_u8","Vector long move."],["vmovn_s16","Vector narrow integer."],["vmovn_s32","Vector narrow integer."],["vmovn_s64","Vector narrow integer."],["vmovn_u16","Vector narrow integer."],["vmovn_u32","Vector narrow integer."],["vmovn_u64","Vector narrow integer."],["vpmax_f32","Folding maximum of adjacent pairs"],["vpmax_s16","Folding maximum of adjacent pairs"],["vpmax_s32","Folding maximum of adjacent pairs"],["vpmax_s8","Folding maximum of adjacent pairs"],["vpmax_u16","Folding maximum of adjacent pairs"],["vpmax_u32","Folding maximum of adjacent pairs"],["vpmax_u8","Folding maximum of adjacent pairs"],["vpmaxq_f32","Folding maximum of adjacent pairs"],["vpmaxq_f64","Folding maximum of adjacent pairs"],["vpmaxq_s16","Folding maximum of adjacent pairs"],["vpmaxq_s32","Folding maximum of adjacent pairs"],["vpmaxq_s8","Folding maximum of adjacent pairs"],["vpmaxq_u16","Folding maximum of adjacent pairs"],["vpmaxq_u32","Folding maximum of adjacent pairs"],["vpmaxq_u8","Folding maximum of adjacent pairs"],["vpmin_f32","Folding minimum of adjacent pairs"],["vpmin_s16","Folding minimum of adjacent pairs"],["vpmin_s32","Folding minimum of adjacent pairs"],["vpmin_s8","Folding minimum of adjacent pairs"],["vpmin_u16","Folding minimum of adjacent pairs"],["vpmin_u32","Folding minimum of adjacent pairs"],["vpmin_u8","Folding minimum of adjacent pairs"],["vpminq_f32","Folding minimum of adjacent pairs"],["vpminq_f64","Folding minimum of adjacent pairs"],["vpminq_s16","Folding minimum of adjacent pairs"],["vpminq_s32","Folding minimum of adjacent pairs"],["vpminq_s8","Folding minimum of adjacent pairs"],["vpminq_u16","Folding minimum of adjacent pairs"],["vpminq_u32","Folding minimum of adjacent pairs"],["vpminq_u8","Folding minimum of adjacent pairs"],["vqtbl1_p8","Table look-up"],["vqtbl1_s8","Table look-up"],["vqtbl1_u8","Table look-up"],["vqtbl1q_p8","Table look-up"],["vqtbl1q_s8","Table look-up"],["vqtbl1q_u8","Table look-up"],["vqtbl2_p8","Table look-up"],["vqtbl2_s8","Table look-up"],["vqtbl2_u8","Table look-up"],["vqtbl2q_p8","Table look-up"],["vqtbl2q_s8","Table look-up"],["vqtbl2q_u8","Table look-up"],["vqtbl3_p8","Table look-up"],["vqtbl3_s8","Table look-up"],["vqtbl3_u8","Table look-up"],["vqtbl3q_p8","Table look-up"],["vqtbl3q_s8","Table look-up"],["vqtbl3q_u8","Table look-up"],["vqtbl4_p8","Table look-up"],["vqtbl4_s8","Table look-up"],["vqtbl4_u8","Table look-up"],["vqtbl4q_p8","Table look-up"],["vqtbl4q_s8","Table look-up"],["vqtbl4q_u8","Table look-up"],["vqtbx1_p8","Extended table look-up"],["vqtbx1_s8","Extended table look-up"],["vqtbx1_u8","Extended table look-up"],["vqtbx1q_p8","Extended table look-up"],["vqtbx1q_s8","Extended table look-up"],["vqtbx1q_u8","Extended table look-up"],["vqtbx2_p8","Extended table look-up"],["vqtbx2_s8","Extended table look-up"],["vqtbx2_u8","Extended table look-up"],["vqtbx2q_p8","Extended table look-up"],["vqtbx2q_s8","Extended table look-up"],["vqtbx2q_u8","Extended table look-up"],["vqtbx3_p8","Extended table look-up"],["vqtbx3_s8","Extended table look-up"],["vqtbx3_u8","Extended table look-up"],["vqtbx3q_p8","Extended table look-up"],["vqtbx3q_s8","Extended table look-up"],["vqtbx3q_u8","Extended table look-up"],["vqtbx4_p8","Extended table look-up"],["vqtbx4_s8","Extended table look-up"],["vqtbx4_u8","Extended table look-up"],["vqtbx4q_p8","Extended table look-up"],["vqtbx4q_s8","Extended table look-up"],["vqtbx4q_u8","Extended table look-up"],["vrsqrte_f32","Reciprocal square-root estimate."],["vsha1cq_u32","SHA1 hash update accelerator, choose."],["vsha1h_u32","SHA1 fixed rotate."],["vsha1mq_u32","SHA1 hash update accelerator, majority."],["vsha1pq_u32","SHA1 hash update accelerator, parity."],["vsha1su0q_u32","SHA1 schedule update accelerator, first part."],["vsha1su1q_u32","SHA1 schedule update accelerator, second part."],["vsha256h2q_u32","SHA256 hash update accelerator, upper part."],["vsha256hq_u32","SHA256 hash update accelerator."],["vsha256su0q_u32","SHA256 schedule update accelerator, first part."],["vsha256su1q_u32","SHA256 schedule update accelerator, second part."],["vtbl1_p8","Table look-up"],["vtbl1_s8","Table look-up"],["vtbl1_u8","Table look-up"],["vtbl2_p8","Table look-up"],["vtbl2_s8","Table look-up"],["vtbl2_u8","Table look-up"],["vtbl3_p8","Table look-up"],["vtbl3_s8","Table look-up"],["vtbl3_u8","Table look-up"],["vtbl4_p8","Table look-up"],["vtbl4_s8","Table look-up"],["vtbl4_u8","Table look-up"],["vtbx1_p8","Extended table look-up"],["vtbx1_s8","Extended table look-up"],["vtbx1_u8","Extended table look-up"],["vtbx2_p8","Extended table look-up"],["vtbx2_s8","Extended table look-up"],["vtbx2_u8","Extended table look-up"],["vtbx3_p8","Extended table look-up"],["vtbx3_s8","Extended table look-up"],["vtbx3_u8","Extended table look-up"],["vtbx4_p8","Extended table look-up"],["vtbx4_s8","Extended table look-up"],["vtbx4_u8","Extended table look-up"]],"struct":[["APSR","Application Program Status Register"],["APSR","Application Program Status Register"],["ISH","Inner Shareable is the required shareability domain, reads and writes are the required access types"],["ISH","Inner Shareable is the required shareability domain, reads and writes are the required access types"],["ISHST","Inner Shareable is the required shareability domain, writes are the required access type"],["ISHST","Inner Shareable is the required shareability domain, writes are the required access type"],["NSH","Non-shareable is the required shareability domain, reads and writes are the required access types"],["NSH","Non-shareable is the required shareability domain, reads and writes are the required access types"],["NSHST","Non-shareable is the required shareability domain, writes are the required access type"],["NSHST","Non-shareable is the required shareability domain, writes are the required access type"],["OSH","Outer Shareable is the required shareability domain, reads and writes are the required access types"],["OSH","Outer Shareable is the required shareability domain, reads and writes are the required access types"],["OSHST","Outer Shareable is the required shareability domain, writes are the required access type"],["OSHST","Outer Shareable is the required shareability domain, writes are the required access type"],["ST","Full system is the required shareability domain, writes are the required access type"],["ST","Full system is the required shareability domain, writes are the required access type"],["SY","Full system is the required shareability domain, reads and writes are the required access types"],["SY","Full system is the required shareability domain, reads and writes are the required access types"],["float32x2_t","ARM-specific 64-bit wide vector of two packed `f32`."],["float32x4_t","ARM-specific 128-bit wide vector of four packed `f32`."],["float64x1_t","ARM-specific 64-bit wide vector of one packed `f64`."],["float64x2_t","ARM-specific 128-bit wide vector of two packed `f64`."],["int16x2_t","ARM-specific 32-bit wide vector of two packed `i16`."],["int16x2_t","ARM-specific 32-bit wide vector of two packed `i16`."],["int16x4_t","ARM-specific 64-bit wide vector of four packed `i16`."],["int16x8_t","ARM-specific 128-bit wide vector of eight packed `i16`."],["int32x2_t","ARM-specific 64-bit wide vector of two packed `i32`."],["int32x4_t","ARM-specific 128-bit wide vector of four packed `i32`."],["int64x1_t","ARM-specific 64-bit wide vector of one packed `i64`."],["int64x2_t","ARM-specific 128-bit wide vector of two packed `i64`."],["int8x16_t","ARM-specific 128-bit wide vector of sixteen packed `i8`."],["int8x16x2_t","ARM-specific type containing two `int8x16_t` vectors."],["int8x16x3_t","ARM-specific type containing three `int8x16_t` vectors."],["int8x16x4_t","ARM-specific type containing four `int8x16_t` vectors."],["int8x4_t","ARM-specific 32-bit wide vector of four packed `i8`."],["int8x4_t","ARM-specific 32-bit wide vector of four packed `i8`."],["int8x8_t","ARM-specific 64-bit wide vector of eight packed `i8`."],["int8x8x2_t","ARM-specific type containing two `int8x8_t` vectors."],["int8x8x3_t","ARM-specific type containing three `int8x8_t` vectors."],["int8x8x4_t","ARM-specific type containing four `int8x8_t` vectors."],["poly16x4_t","ARM-specific 64-bit wide vector of four packed `u16`."],["poly16x8_t","ARM-specific 128-bit wide vector of eight packed `u16`."],["poly64x1_t","ARM-specific 64-bit wide vector of one packed `p64`."],["poly64x2_t","ARM-specific 64-bit wide vector of two packed `p64`."],["poly8x16_t","ARM-specific 128-bit wide vector of sixteen packed `u8`."],["poly8x16x2_t","ARM-specific type containing two `poly8x16_t` vectors."],["poly8x16x3_t","ARM-specific type containing three `poly8x16_t` vectors."],["poly8x16x4_t","ARM-specific type containing four `poly8x16_t` vectors."],["poly8x8_t","ARM-specific 64-bit wide polynomial vector of eight packed `u8`."],["poly8x8x2_t","ARM-specific type containing two `poly8x8_t` vectors."],["poly8x8x3_t","ARM-specific type containing three `poly8x8_t` vectors."],["poly8x8x4_t","ARM-specific type containing four `poly8x8_t` vectors."],["uint16x2_t","ARM-specific 32-bit wide vector of two packed `u16`."],["uint16x2_t","ARM-specific 32-bit wide vector of two packed `u16`."],["uint16x4_t","ARM-specific 64-bit wide vector of four packed `u16`."],["uint16x8_t","ARM-specific 128-bit wide vector of eight packed `u16`."],["uint32x2_t","ARM-specific 64-bit wide vector of two packed `u32`."],["uint32x4_t","ARM-specific 128-bit wide vector of four packed `u32`."],["uint64x1_t","ARM-specific 64-bit wide vector of one packed `u64`."],["uint64x2_t","ARM-specific 128-bit wide vector of two packed `u64`."],["uint8x16_t","ARM-specific 128-bit wide vector of sixteen packed `u8`."],["uint8x16x2_t","ARM-specific type containing two `uint8x16_t` vectors."],["uint8x16x3_t","ARM-specific type containing three `uint8x16_t` vectors."],["uint8x16x4_t","ARM-specific type containing four `uint8x16_t` vectors."],["uint8x4_t","ARM-specific 32-bit wide vector of four packed `u8`."],["uint8x4_t","ARM-specific 32-bit wide vector of four packed `u8`."],["uint8x8_t","ARM-specific 64-bit wide vector of eight packed `u8`."],["uint8x8x2_t","ARM-specific type containing two `uint8x8_t` vectors."],["uint8x8x3_t","ARM-specific type containing three `uint8x8_t` vectors."],["uint8x8x4_t","ARM-specific type containing four `uint8x8_t` vectors."]]});