--- a/js/src/jit/x86-shared/Assembler-x86-shared.cpp	2019-05-21 19:30:05.036892727 +0100
+++ b/js/src/jit/x86-shared/Assembler-x86-shared.cpp	2019-05-21 19:31:26.805437074 +0100
@@ -340,12 +340,14 @@
     avxPresent = (xcr0EAX & xcr0SSEBit) && (xcr0EAX & xcr0AVXBit);
   }
 
+ if (maxSSEVersion >= SSE2) {
   // CMOV instruction are supposed to be supported by all CPU which have SSE2
   // enabled. While this might be true, this is not guaranteed by any
   // documentation, nor AMD, nor Intel.
   static const int CMOVBit = 1 << 15;
   MOZ_RELEASE_ASSERT(flagsEDX & CMOVBit,
                      "CMOVcc instruction is not recognized by this CPU.");
+ }
 
   static const int POPCNTBit = 1 << 23;
   popcntPresent = (flagsECX & POPCNTBit);