Microsemi Ocelot network Switch
===============================

The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
VSC7514)

Required properties:
- compatible: Should be "mscc,vsc7514-switch"
- reg: Must contain an (offset, length) pair of the register set for each
  entry in reg-names.
- reg-names: Must include the following entries:
  - "sys"
  - "rew"
  - "qs"
  - "qsys"
  - "ana"
  - "portX" with X from 0 to the number of last port index available on that
    switch
- interrupts: Should contain the switch interrupts for frame extraction and
  frame injection
- interrupt-names: should contain the interrupt names: "xtr", "inj"
- ethernet-ports: A container for child nodes representing switch ports.

The ethernet-ports container has the following properties

Required properties:

- #address-cells: Must be 1
- #size-cells: Must be 0

Each port node must have the following mandatory properties:
- reg: Describes the port address in the switch

Port nodes may also contain the following optional standardised
properties, described in binding documents:

- phy-handle: Phandle to a PHY on an MDIO bus. See
  Documentation/devicetree/bindings/net/ethernet.txt for details.

Example:

	switch@1010000 {
		compatible = "mscc,vsc7514-switch";
		reg = <0x1010000 0x10000>,
		      <0x1030000 0x10000>,
		      <0x1080000 0x100>,
		      <0x11e0000 0x100>,
		      <0x11f0000 0x100>,
		      <0x1200000 0x100>,
		      <0x1210000 0x100>,
		      <0x1220000 0x100>,
		      <0x1230000 0x100>,
		      <0x1240000 0x100>,
		      <0x1250000 0x100>,
		      <0x1260000 0x100>,
		      <0x1270000 0x100>,
		      <0x1280000 0x100>,
		      <0x1800000 0x80000>,
		      <0x1880000 0x10000>;
		reg-names = "sys", "rew", "qs", "port0", "port1", "port2",
			    "port3", "port4", "port5", "port6", "port7",
			    "port8", "port9", "port10", "qsys", "ana";
		interrupts = <21 22>;
		interrupt-names = "xtr", "inj";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port0: port@0 {
				reg = <0>;
				phy-handle = <&phy0>;
			};
			port1: port@1 {
				reg = <1>;
				phy-handle = <&phy1>;
			};
		};
	};