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<div class="section" id="machine-ir-mir-format-reference-manual">
<h1>Machine IR (MIR) Format Reference Manual<a class="headerlink" href="#machine-ir-mir-format-reference-manual" title="Permalink to this headline">¶</a></h1>
<div class="contents local topic" id="contents">
<ul class="simple">
<li><a class="reference internal" href="#introduction" id="id10">Introduction</a></li>
<li><a class="reference internal" href="#overview" id="id11">Overview</a></li>
<li><a class="reference internal" href="#mir-testing-guide" id="id12">MIR Testing Guide</a><ul>
<li><a class="reference internal" href="#testing-individual-code-generation-passes" id="id13">Testing Individual Code Generation Passes</a><ul>
<li><a class="reference internal" href="#simplifying-mir-files" id="id14">Simplifying MIR files</a></li>
</ul>
</li>
<li><a class="reference internal" href="#limitations" id="id15">Limitations</a></li>
</ul>
</li>
<li><a class="reference internal" href="#high-level-structure" id="id16">High Level Structure</a><ul>
<li><a class="reference internal" href="#embedded-module" id="id17">Embedded Module</a></li>
<li><a class="reference internal" href="#machine-functions" id="id18">Machine Functions</a></li>
</ul>
</li>
<li><a class="reference internal" href="#machine-instructions-format-reference" id="id19">Machine Instructions Format Reference</a><ul>
<li><a class="reference internal" href="#machine-basic-blocks" id="id20">Machine Basic Blocks</a><ul>
<li><a class="reference internal" href="#block-references" id="id21">Block References</a></li>
<li><a class="reference internal" href="#successors" id="id22">Successors</a></li>
<li><a class="reference internal" href="#live-in-registers" id="id23">Live In Registers</a></li>
<li><a class="reference internal" href="#miscellaneous-attributes" id="id24">Miscellaneous Attributes</a></li>
</ul>
</li>
<li><a class="reference internal" href="#machine-instructions" id="id25">Machine Instructions</a><ul>
<li><a class="reference internal" href="#instruction-flags" id="id26">Instruction Flags</a></li>
<li><a class="reference internal" href="#bundled-instructions" id="id27">Bundled Instructions</a></li>
</ul>
</li>
<li><a class="reference internal" href="#id5" id="id28">Registers</a></li>
<li><a class="reference internal" href="#machine-operands" id="id29">Machine Operands</a><ul>
<li><a class="reference internal" href="#immediate-operands" id="id30">Immediate Operands</a></li>
<li><a class="reference internal" href="#register-operands" id="id31">Register Operands</a><ul>
<li><a class="reference internal" href="#register-flags" id="id32">Register Flags</a></li>
<li><a class="reference internal" href="#subregister-indices" id="id33">Subregister Indices</a></li>
</ul>
</li>
<li><a class="reference internal" href="#constant-pool-indices" id="id34">Constant Pool Indices</a></li>
<li><a class="reference internal" href="#global-value-operands" id="id35">Global Value Operands</a></li>
<li><a class="reference internal" href="#target-dependent-index-operands" id="id36">Target-dependent Index Operands</a></li>
<li><a class="reference internal" href="#jump-table-index-operands" id="id37">Jump-table Index Operands</a></li>
<li><a class="reference internal" href="#external-symbol-operands" id="id38">External Symbol Operands</a></li>
<li><a class="reference internal" href="#mcsymbol-operands" id="id39">MCSymbol Operands</a></li>
<li><a class="reference internal" href="#cfiindex-operands" id="id40">CFIIndex Operands</a></li>
<li><a class="reference internal" href="#intrinsicid-operands" id="id41">IntrinsicID Operands</a></li>
<li><a class="reference internal" href="#predicate-operands" id="id42">Predicate Operands</a></li>
</ul>
</li>
</ul>
</li>
</ul>
</div>
<div class="admonition warning">
<p class="first admonition-title">Warning</p>
<p class="last">This is a work in progress.</p>
</div>
<div class="section" id="introduction">
<h2><a class="toc-backref" href="#id10">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
<p>This document is a reference manual for the Machine IR (MIR) serialization
format. MIR is a human readable serialization format that is used to represent
LLVM’s <a class="reference internal" href="CodeGenerator.html#machine-code-representation"><span class="std std-ref">machine specific intermediate representation</span></a>.</p>
<p>The MIR serialization format is designed to be used for testing the code
generation passes in LLVM.</p>
</div>
<div class="section" id="overview">
<h2><a class="toc-backref" href="#id11">Overview</a><a class="headerlink" href="#overview" title="Permalink to this headline">¶</a></h2>
<p>The MIR serialization format uses a YAML container. YAML is a standard
data serialization language, and the full YAML language spec can be read at
<a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html#Introduction">yaml.org</a>.</p>
<p>A MIR file is split up into a series of <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html#id2800132">YAML documents</a>. The first document
can contain an optional embedded LLVM IR module, and the rest of the documents
contain the serialized machine functions.</p>
</div>
<div class="section" id="mir-testing-guide">
<h2><a class="toc-backref" href="#id12">MIR Testing Guide</a><a class="headerlink" href="#mir-testing-guide" title="Permalink to this headline">¶</a></h2>
<p>You can use the MIR format for testing in two different ways:</p>
<ul class="simple">
<li>You can write MIR tests that invoke a single code generation pass using the
<code class="docutils literal notranslate"><span class="pre">-run-pass</span></code> option in llc.</li>
<li>You can use llc’s <code class="docutils literal notranslate"><span class="pre">-stop-after</span></code> option with existing or new LLVM assembly
tests and check the MIR output of a specific code generation pass.</li>
</ul>
<div class="section" id="testing-individual-code-generation-passes">
<h3><a class="toc-backref" href="#id13">Testing Individual Code Generation Passes</a><a class="headerlink" href="#testing-individual-code-generation-passes" title="Permalink to this headline">¶</a></h3>
<p>The <code class="docutils literal notranslate"><span class="pre">-run-pass</span></code> option in llc allows you to create MIR tests that invoke just
a single code generation pass. When this option is used, llc will parse an
input MIR file, run the specified code generation pass(es), and output the
resulting MIR code.</p>
<p>You can generate an input MIR file for the test by using the <code class="docutils literal notranslate"><span class="pre">-stop-after</span></code> or
<code class="docutils literal notranslate"><span class="pre">-stop-before</span></code> option in llc. For example, if you would like to write a test
for the post register allocation pseudo instruction expansion pass, you can
specify the machine copy propagation pass in the <code class="docutils literal notranslate"><span class="pre">-stop-after</span></code> option, as it
runs just before the pass that we are trying to test:</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre">llc</span> <span class="pre">-stop-after=machine-cp</span> <span class="pre">bug-trigger.ll</span> <span class="pre">></span> <span class="pre">test.mir</span></code></div></blockquote>
<p>If the same pass is run multiple times, a run index can be included
after the name with a comma.</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre">llc</span> <span class="pre">-stop-after=dead-mi-elimination,1</span> <span class="pre">bug-trigger.ll</span> <span class="pre">></span> <span class="pre">test.mir</span></code></div></blockquote>
<p>After generating the input MIR file, you’ll have to add a run line that uses
the <code class="docutils literal notranslate"><span class="pre">-run-pass</span></code> option to it. In order to test the post register allocation
pseudo instruction expansion pass on X86-64, a run line like the one shown
below can be used:</p>
<blockquote>
<div><code class="docutils literal notranslate"><span class="pre">#</span> <span class="pre">RUN:</span> <span class="pre">llc</span> <span class="pre">-o</span> <span class="pre">-</span> <span class="pre">%s</span> <span class="pre">-mtriple=x86_64--</span> <span class="pre">-run-pass=postrapseudos</span> <span class="pre">|</span> <span class="pre">FileCheck</span> <span class="pre">%s</span></code></div></blockquote>
<p>The MIR files are target dependent, so they have to be placed in the target
specific test directories (<code class="docutils literal notranslate"><span class="pre">lib/CodeGen/TARGETNAME</span></code>). They also need to
specify a target triple or a target architecture either in the run line or in
the embedded LLVM IR module.</p>
<div class="section" id="simplifying-mir-files">
<h4><a class="toc-backref" href="#id14">Simplifying MIR files</a><a class="headerlink" href="#simplifying-mir-files" title="Permalink to this headline">¶</a></h4>
<p>The MIR code coming out of <code class="docutils literal notranslate"><span class="pre">-stop-after</span></code>/<code class="docutils literal notranslate"><span class="pre">-stop-before</span></code> is very verbose;
Tests are more accessible and future proof when simplified:</p>
<ul class="simple">
<li>Use the <code class="docutils literal notranslate"><span class="pre">-simplify-mir</span></code> option with llc.</li>
<li>Machine function attributes often have default values or the test works just
as well with default values. Typical candidates for this are: <cite>alignment:</cite>,
<cite>exposesReturnsTwice</cite>, <cite>legalized</cite>, <cite>regBankSelected</cite>, <cite>selected</cite>.
The whole <cite>frameInfo</cite> section is often unnecessary if there is no special
frame usage in the function. <cite>tracksRegLiveness</cite> on the other hand is often
necessary for some passes that care about block livein lists.</li>
<li>The (global) <cite>liveins:</cite> list is typically only interesting for early
instruction selection passes and can be removed when testing later passes.
The per-block <cite>liveins:</cite> on the other hand are necessary if
<cite>tracksRegLiveness</cite> is true.</li>
<li>Branch probability data in block <cite>successors:</cite> lists can be dropped if the
test doesn’t depend on it. Example:
<cite>successors: %bb.1(0x40000000), %bb.2(0x40000000)</cite> can be replaced with
<cite>successors: %bb.1, %bb.2</cite>.</li>
<li>MIR code contains a whole IR module. This is necessary because there are
no equivalents in MIR for global variables, references to external functions,
function attributes, metadata, debug info. Instead some MIR data references
the IR constructs. You can often remove them if the test doesn’t depend on
them.</li>
<li>Alias Analysis is performed on IR values. These are referenced by memory
operands in MIR. Example: <cite>:: (load 8 from %ir.foobar, !alias.scope !9)</cite>.
If the test doesn’t depend on (good) alias analysis the references can be
dropped: <cite>:: (load 8)</cite></li>
<li>MIR blocks can reference IR blocks for debug printing, profile information
or debug locations. Example: <cite>bb.42.myblock</cite> in MIR references the IR block
<cite>myblock</cite>. It is usually possible to drop the <cite>.myblock</cite> reference and simply
use <cite>bb.42</cite>.</li>
<li>If there are no memory operands or blocks referencing the IR then the
IR function can be replaced by a parameterless dummy function like
<cite>define @func() { ret void }</cite>.</li>
<li>It is possible to drop the whole IR section of the MIR file if it only
contains dummy functions (see above). The .mir loader will create the
IR functions automatically in this case.</li>
</ul>
</div>
</div>
<div class="section" id="limitations">
<span id="id1"></span><h3><a class="toc-backref" href="#id15">Limitations</a><a class="headerlink" href="#limitations" title="Permalink to this headline">¶</a></h3>
<p>Currently the MIR format has several limitations in terms of which state it
can serialize:</p>
<ul class="simple">
<li>The target-specific state in the target-specific <code class="docutils literal notranslate"><span class="pre">MachineFunctionInfo</span></code>
subclasses isn’t serialized at the moment.</li>
<li>The target-specific <code class="docutils literal notranslate"><span class="pre">MachineConstantPoolValue</span></code> subclasses (in the ARM and
SystemZ backends) aren’t serialized at the moment.</li>
<li>The <code class="docutils literal notranslate"><span class="pre">MCSymbol</span></code> machine operands don’t support temporary or local symbols.</li>
<li>A lot of the state in <code class="docutils literal notranslate"><span class="pre">MachineModuleInfo</span></code> isn’t serialized - only the CFI
instructions and the variable debug information from MMI is serialized right
now.</li>
</ul>
<p>These limitations impose restrictions on what you can test with the MIR format.
For now, tests that would like to test some behaviour that depends on the state
of temporary or local <code class="docutils literal notranslate"><span class="pre">MCSymbol</span></code> operands or the exception handling state in
MMI, can’t use the MIR format. As well as that, tests that test some behaviour
that depends on the state of the target specific <code class="docutils literal notranslate"><span class="pre">MachineFunctionInfo</span></code> or
<code class="docutils literal notranslate"><span class="pre">MachineConstantPoolValue</span></code> subclasses can’t use the MIR format at the moment.</p>
</div>
</div>
<div class="section" id="high-level-structure">
<h2><a class="toc-backref" href="#id16">High Level Structure</a><a class="headerlink" href="#high-level-structure" title="Permalink to this headline">¶</a></h2>
<div class="section" id="embedded-module">
<span id="id2"></span><h3><a class="toc-backref" href="#id17">Embedded Module</a><a class="headerlink" href="#embedded-module" title="Permalink to this headline">¶</a></h3>
<p>When the first YAML document contains a <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html#id2795688">YAML block literal string</a>, the MIR
parser will treat this string as an LLVM assembly language string that
represents an embedded LLVM IR module.
Here is an example of a YAML document that contains an LLVM module:</p>
<div class="highlight-llvm notranslate"><div class="highlight"><pre><span></span><span class="k">define</span> <span class="k">i32</span> <span class="vg">@inc</span><span class="p">(</span><span class="k">i32</span><span class="p">*</span> <span class="nv">%x</span><span class="p">)</span> <span class="p">{</span>
<span class="nl">entry:</span>
<span class="nv nv-Anonymous">%0</span> <span class="p">=</span> <span class="k">load</span> <span class="k">i32</span><span class="p">,</span> <span class="k">i32</span><span class="p">*</span> <span class="nv">%x</span>
<span class="nv nv-Anonymous">%1</span> <span class="p">=</span> <span class="k">add</span> <span class="k">i32</span> <span class="nv nv-Anonymous">%0</span><span class="p">,</span> <span class="m">1</span>
<span class="k">store</span> <span class="k">i32</span> <span class="nv nv-Anonymous">%1</span><span class="p">,</span> <span class="k">i32</span><span class="p">*</span> <span class="nv">%x</span>
<span class="k">ret</span> <span class="k">i32</span> <span class="nv nv-Anonymous">%1</span>
<span class="p">}</span>
</pre></div>
</div>
</div>
<div class="section" id="machine-functions">
<h3><a class="toc-backref" href="#id18">Machine Functions</a><a class="headerlink" href="#machine-functions" title="Permalink to this headline">¶</a></h3>
<p>The remaining YAML documents contain the machine functions. This is an example
of such YAML document:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>---
name: inc
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
body: |
bb.0.entry:
liveins: $rdi
$eax = MOV32rm $rdi, 1, _, 0, _
$eax = INC32r killed $eax, implicit-def dead $eflags
MOV32mr killed $rdi, 1, _, 0, _, $eax
RETQ $eax
...
</pre></div>
</div>
<p>The document above consists of attributes that represent the various
properties and data structures in a machine function.</p>
<p>The attribute <code class="docutils literal notranslate"><span class="pre">name</span></code> is required, and its value should be identical to the
name of a function that this machine function is based on.</p>
<p>The attribute <code class="docutils literal notranslate"><span class="pre">body</span></code> is a <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html#id2795688">YAML block literal string</a>. Its value represents
the function’s machine basic blocks and their machine instructions.</p>
</div>
</div>
<div class="section" id="machine-instructions-format-reference">
<h2><a class="toc-backref" href="#id19">Machine Instructions Format Reference</a><a class="headerlink" href="#machine-instructions-format-reference" title="Permalink to this headline">¶</a></h2>
<p>The machine basic blocks and their instructions are represented using a custom,
human readable serialization language. This language is used in the
<a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html#id2795688">YAML block literal string</a> that corresponds to the machine function’s body.</p>
<p>A source string that uses this language contains a list of machine basic
blocks, which are described in the section below.</p>
<div class="section" id="machine-basic-blocks">
<h3><a class="toc-backref" href="#id20">Machine Basic Blocks</a><a class="headerlink" href="#machine-basic-blocks" title="Permalink to this headline">¶</a></h3>
<p>A machine basic block is defined in a single block definition source construct
that contains the block’s ID.
The example below defines two blocks that have an ID of zero and one:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>bb.0:
<instructions>
bb.1:
<instructions>
</pre></div>
</div>
<p>A machine basic block can also have a name. It should be specified after the ID
in the block’s definition:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>bb.0.entry: ; This block's name is "entry"
<instructions>
</pre></div>
</div>
<p>The block’s name should be identical to the name of the IR block that this
machine block is based on.</p>
<div class="section" id="block-references">
<span id="id3"></span><h4><a class="toc-backref" href="#id21">Block References</a><a class="headerlink" href="#block-references" title="Permalink to this headline">¶</a></h4>
<p>The machine basic blocks are identified by their ID numbers. Individual
blocks are referenced using the following syntax:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%bb.<id>
</pre></div>
</div>
<p>Example:</p>
<div class="highlight-llvm notranslate"><div class="highlight"><pre><span></span><span class="nv">%bb.0</span>
</pre></div>
</div>
<p>The following syntax is also supported, but the former syntax is preferred for
block references:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%bb.<id>[.<name>]
</pre></div>
</div>
<p>Example:</p>
<div class="highlight-llvm notranslate"><div class="highlight"><pre><span></span><span class="nv">%bb.1.then</span>
</pre></div>
</div>
</div>
<div class="section" id="successors">
<h4><a class="toc-backref" href="#id22">Successors</a><a class="headerlink" href="#successors" title="Permalink to this headline">¶</a></h4>
<p>The machine basic block’s successors have to be specified before any of the
instructions:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>bb.0.entry:
successors: %bb.1.then, %bb.2.else
<instructions>
bb.1.then:
<instructions>
bb.2.else:
<instructions>
</pre></div>
</div>
<p>The branch weights can be specified in brackets after the successor blocks.
The example below defines a block that has two successors with branch weights
of 32 and 16:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>bb.0.entry:
successors: %bb.1.then(32), %bb.2.else(16)
</pre></div>
</div>
</div>
<div class="section" id="live-in-registers">
<span id="bb-liveins"></span><h4><a class="toc-backref" href="#id23">Live In Registers</a><a class="headerlink" href="#live-in-registers" title="Permalink to this headline">¶</a></h4>
<p>The machine basic block’s live in registers have to be specified before any of
the instructions:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>bb.0.entry:
liveins: $edi, $esi
</pre></div>
</div>
<p>The list of live in registers and successors can be empty. The language also
allows multiple live in register and successor lists - they are combined into
one list by the parser.</p>
</div>
<div class="section" id="miscellaneous-attributes">
<h4><a class="toc-backref" href="#id24">Miscellaneous Attributes</a><a class="headerlink" href="#miscellaneous-attributes" title="Permalink to this headline">¶</a></h4>
<p>The attributes <code class="docutils literal notranslate"><span class="pre">IsAddressTaken</span></code>, <code class="docutils literal notranslate"><span class="pre">IsLandingPad</span></code> and <code class="docutils literal notranslate"><span class="pre">Alignment</span></code> can be
specified in brackets after the block’s definition:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>bb.0.entry (address-taken):
<instructions>
bb.2.else (align 4):
<instructions>
bb.3(landing-pad, align 4):
<instructions>
</pre></div>
</div>
</div>
</div>
<div class="section" id="machine-instructions">
<h3><a class="toc-backref" href="#id25">Machine Instructions</a><a class="headerlink" href="#machine-instructions" title="Permalink to this headline">¶</a></h3>
<p>A machine instruction is composed of a name,
<a class="reference internal" href="#machine-operands"><span class="std std-ref">machine operands</span></a>,
<a class="reference internal" href="#instruction-flags"><span class="std std-ref">instruction flags</span></a>, and machine memory operands.</p>
<p>The instruction’s name is usually specified before the operands. The example
below shows an instance of the X86 <code class="docutils literal notranslate"><span class="pre">RETQ</span></code> instruction with a single machine
operand:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>RETQ $eax
</pre></div>
</div>
<p>However, if the machine instruction has one or more explicitly defined register
operands, the instruction’s name has to be specified after them. The example
below shows an instance of the AArch64 <code class="docutils literal notranslate"><span class="pre">LDPXpost</span></code> instruction with three
defined register operands:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$sp, $fp, $lr = LDPXpost $sp, 2
</pre></div>
</div>
<p>The instruction names are serialized using the exact definitions from the
target’s <code class="docutils literal notranslate"><span class="pre">*InstrInfo.td</span></code> files, and they are case sensitive. This means that
similar instruction names like <code class="docutils literal notranslate"><span class="pre">TSTri</span></code> and <code class="docutils literal notranslate"><span class="pre">tSTRi</span></code> represent different
machine instructions.</p>
<div class="section" id="instruction-flags">
<span id="id4"></span><h4><a class="toc-backref" href="#id26">Instruction Flags</a><a class="headerlink" href="#instruction-flags" title="Permalink to this headline">¶</a></h4>
<p>The flag <code class="docutils literal notranslate"><span class="pre">frame-setup</span></code> or <code class="docutils literal notranslate"><span class="pre">frame-destroy</span></code> can be specified before the
instruction’s name:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$fp = frame-setup ADDXri $sp, 0, 0
</pre></div>
</div>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$x21, $x20 = frame-destroy LDPXi $sp
</pre></div>
</div>
</div>
<div class="section" id="bundled-instructions">
<span id="registers"></span><h4><a class="toc-backref" href="#id27">Bundled Instructions</a><a class="headerlink" href="#bundled-instructions" title="Permalink to this headline">¶</a></h4>
<p>The syntax for bundled instructions is the following:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>BUNDLE implicit-def $r0, implicit-def $r1, implicit $r2 {
$r0 = SOME_OP $r2
$r1 = ANOTHER_OP internal $r0
}
</pre></div>
</div>
<p>The first instruction is often a bundle header. The instructions between <code class="docutils literal notranslate"><span class="pre">{</span></code>
and <code class="docutils literal notranslate"><span class="pre">}</span></code> are bundled with the first instruction.</p>
</div>
</div>
<div class="section" id="id5">
<h3><a class="toc-backref" href="#id28">Registers</a><a class="headerlink" href="#id5" title="Permalink to this headline">¶</a></h3>
<p>Registers are one of the key primitives in the machine instructions
serialization language. They are primarily used in the
<a class="reference internal" href="#register-operands"><span class="std std-ref">register machine operands</span></a>,
but they can also be used in a number of other places, like the
<a class="reference internal" href="#bb-liveins"><span class="std std-ref">basic block’s live in list</span></a>.</p>
<p>The physical registers are identified by their name and by the ‘$’ prefix sigil.
They use the following syntax:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$<name>
</pre></div>
</div>
<p>The example below shows three X86 physical registers:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$eax
$r15
$eflags
</pre></div>
</div>
<p>The virtual registers are identified by their ID number and by the ‘%’ sigil.
They use the following syntax:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%<id>
</pre></div>
</div>
<p>Example:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%0
</pre></div>
</div>
<p>The null registers are represented using an underscore (‘<code class="docutils literal notranslate"><span class="pre">_</span></code>’). They can also be
represented using a ‘<code class="docutils literal notranslate"><span class="pre">$noreg</span></code>’ named register, although the former syntax
is preferred.</p>
</div>
<div class="section" id="machine-operands">
<span id="id6"></span><h3><a class="toc-backref" href="#id29">Machine Operands</a><a class="headerlink" href="#machine-operands" title="Permalink to this headline">¶</a></h3>
<p>There are seventeen different kinds of machine operands, and all of them can be
serialized.</p>
<div class="section" id="immediate-operands">
<h4><a class="toc-backref" href="#id30">Immediate Operands</a><a class="headerlink" href="#immediate-operands" title="Permalink to this headline">¶</a></h4>
<p>The immediate machine operands are untyped, 64-bit signed integers. The
example below shows an instance of the X86 <code class="docutils literal notranslate"><span class="pre">MOV32ri</span></code> instruction that has an
immediate machine operand <code class="docutils literal notranslate"><span class="pre">-42</span></code>:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$eax = MOV32ri -42
</pre></div>
</div>
<p>An immediate operand is also used to represent a subregister index when the
machine instruction has one of the following opcodes:</p>
<ul class="simple">
<li><code class="docutils literal notranslate"><span class="pre">EXTRACT_SUBREG</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">INSERT_SUBREG</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">REG_SEQUENCE</span></code></li>
<li><code class="docutils literal notranslate"><span class="pre">SUBREG_TO_REG</span></code></li>
</ul>
<p>In case this is true, the Machine Operand is printed according to the target.</p>
<p>For example:</p>
<p>In AArch64RegisterInfo.td:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>def sub_32 : SubRegIndex<32>;
</pre></div>
</div>
<p>If the third operand is an immediate with the value <code class="docutils literal notranslate"><span class="pre">15</span></code> (target-dependent
value), based on the instruction’s opcode and the operand’s index the operand
will be printed as <code class="docutils literal notranslate"><span class="pre">%subreg.sub_32</span></code>:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
</pre></div>
</div>
<p>For integers > 64bit, we use a special machine operand, <code class="docutils literal notranslate"><span class="pre">MO_CImmediate</span></code>,
which stores the immediate in a <code class="docutils literal notranslate"><span class="pre">ConstantInt</span></code> using an <code class="docutils literal notranslate"><span class="pre">APInt</span></code> (LLVM’s
arbitrary precision integers).</p>
</div>
<div class="section" id="register-operands">
<span id="id7"></span><h4><a class="toc-backref" href="#id31">Register Operands</a><a class="headerlink" href="#register-operands" title="Permalink to this headline">¶</a></h4>
<p>The <a class="reference internal" href="#registers"><span class="std std-ref">register</span></a> primitive is used to represent the register
machine operands. The register operands can also have optional
<a class="reference internal" href="#register-flags"><span class="std std-ref">register flags</span></a>,
<a class="reference internal" href="#subregister-indices"><span class="std std-ref">a subregister index</span></a>,
and a reference to the tied register operand.
The full syntax of a register operand is shown below:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>[<flags>] <register> [ :<subregister-idx-name> ] [ (tied-def <tied-op>) ]
</pre></div>
</div>
<p>This example shows an instance of the X86 <code class="docutils literal notranslate"><span class="pre">XOR32rr</span></code> instruction that has
5 register operands with different register flags:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
</pre></div>
</div>
<div class="section" id="register-flags">
<span id="id8"></span><h5><a class="toc-backref" href="#id32">Register Flags</a><a class="headerlink" href="#register-flags" title="Permalink to this headline">¶</a></h5>
<p>The table below shows all of the possible register flags along with the
corresponding internal <code class="docutils literal notranslate"><span class="pre">llvm::RegState</span></code> representation:</p>
<table border="1" class="docutils">
<colgroup>
<col width="50%" />
<col width="50%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">Flag</th>
<th class="head">Internal Value</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">implicit</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Implicit</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">implicit-def</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::ImplicitDefine</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">def</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Define</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">dead</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Dead</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">killed</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Kill</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">undef</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Undef</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">internal</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::InternalRead</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">early-clobber</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::EarlyClobber</span></code></td>
</tr>
<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">debug-use</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Debug</span></code></td>
</tr>
<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">renamable</span></code></td>
<td><code class="docutils literal notranslate"><span class="pre">RegState::Renamable</span></code></td>
</tr>
</tbody>
</table>
</div>
<div class="section" id="subregister-indices">
<span id="id9"></span><h5><a class="toc-backref" href="#id33">Subregister Indices</a><a class="headerlink" href="#subregister-indices" title="Permalink to this headline">¶</a></h5>
<p>The register machine operands can reference a portion of a register by using
the subregister indices. The example below shows an instance of the <code class="docutils literal notranslate"><span class="pre">COPY</span></code>
pseudo instruction that uses the X86 <code class="docutils literal notranslate"><span class="pre">sub_8bit</span></code> subregister index to copy 8
lower bits from the 32-bit virtual register 0 to the 8-bit virtual register 1:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%1 = COPY %0:sub_8bit
</pre></div>
</div>
<p>The names of the subregister indices are target specific, and are typically
defined in the target’s <code class="docutils literal notranslate"><span class="pre">*RegisterInfo.td</span></code> file.</p>
</div>
</div>
<div class="section" id="constant-pool-indices">
<h4><a class="toc-backref" href="#id34">Constant Pool Indices</a><a class="headerlink" href="#constant-pool-indices" title="Permalink to this headline">¶</a></h4>
<p>A constant pool index (CPI) operand is printed using its index in the
function’s <code class="docutils literal notranslate"><span class="pre">MachineConstantPool</span></code> and an offset.</p>
<p>For example, a CPI with the index 1 and offset 8:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%1:gr64 = MOV64ri %const.1 + 8
</pre></div>
</div>
<p>For a CPI with the index 0 and offset -12:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%1:gr64 = MOV64ri %const.0 - 12
</pre></div>
</div>
<p>A constant pool entry is bound to a LLVM IR <code class="docutils literal notranslate"><span class="pre">Constant</span></code> or a target-specific
<code class="docutils literal notranslate"><span class="pre">MachineConstantPoolValue</span></code>. When serializing all the function’s constants the
following format is used:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>constants:
- id: <index>
value: <value>
alignment: <alignment>
isTargetSpecific: <target-specific>
</pre></div>
</div>
<p>where <code class="docutils literal notranslate"><span class="pre"><index></span></code> is a 32-bit unsigned integer, <code class="docutils literal notranslate"><span class="pre"><value></span></code> is a <a class="reference external" href="https://www.llvm.org/docs/LangRef.html#constants">LLVM IR Constant</a>, alignment is a 32-bit
unsigned integer, and <code class="docutils literal notranslate"><span class="pre"><target-specific></span></code> is either true or false.</p>
<p>Example:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>constants:
- id: 0
value: 'double 3.250000e+00'
alignment: 8
- id: 1
value: 'g-(LPC0+8)'
alignment: 4
isTargetSpecific: true
</pre></div>
</div>
</div>
<div class="section" id="global-value-operands">
<h4><a class="toc-backref" href="#id35">Global Value Operands</a><a class="headerlink" href="#global-value-operands" title="Permalink to this headline">¶</a></h4>
<p>The global value machine operands reference the global values from the
<a class="reference internal" href="#embedded-module"><span class="std std-ref">embedded LLVM IR module</span></a>.
The example below shows an instance of the X86 <code class="docutils literal notranslate"><span class="pre">MOV64rm</span></code> instruction that has
a global value operand named <code class="docutils literal notranslate"><span class="pre">G</span></code>:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$rax = MOV64rm $rip, 1, _, @G, _
</pre></div>
</div>
<p>The named global values are represented using an identifier with the ‘@’ prefix.
If the identifier doesn’t match the regular expression
<cite>[-a-zA-Z$._][-a-zA-Z$._0-9]*</cite>, then this identifier must be quoted.</p>
<p>The unnamed global values are represented using an unsigned numeric value with
the ‘@’ prefix, like in the following examples: <code class="docutils literal notranslate"><span class="pre">@0</span></code>, <code class="docutils literal notranslate"><span class="pre">@989</span></code>.</p>
</div>
<div class="section" id="target-dependent-index-operands">
<h4><a class="toc-backref" href="#id36">Target-dependent Index Operands</a><a class="headerlink" href="#target-dependent-index-operands" title="Permalink to this headline">¶</a></h4>
<p>A target index operand is a target-specific index and an offset. The
target-specific index is printed using target-specific names and a positive or
negative offset.</p>
<p>For example, the <code class="docutils literal notranslate"><span class="pre">amdgpu-constdata-start</span></code> is associated with the index <code class="docutils literal notranslate"><span class="pre">0</span></code>
in the AMDGPU backend. So if we have a target index operand with the index 0
and the offset 8:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$sgpr2 = S_ADD_U32 _, target-index(amdgpu-constdata-start) + 8, implicit-def _, implicit-def _
</pre></div>
</div>
</div>
<div class="section" id="jump-table-index-operands">
<h4><a class="toc-backref" href="#id37">Jump-table Index Operands</a><a class="headerlink" href="#jump-table-index-operands" title="Permalink to this headline">¶</a></h4>
<p>A jump-table index operand with the index 0 is printed as following:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>tBR_JTr killed $r0, %jump-table.0
</pre></div>
</div>
<p>A machine jump-table entry contains a list of <code class="docutils literal notranslate"><span class="pre">MachineBasicBlocks</span></code>. When serializing all the function’s jump-table entries, the following format is used:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>jumpTable:
kind: <kind>
entries:
- id: <index>
blocks: [ <bbreference>, <bbreference>, ... ]
</pre></div>
</div>
<p>where <code class="docutils literal notranslate"><span class="pre"><kind></span></code> is describing how the jump table is represented and emitted (plain address, relocations, PIC, etc.), and each <code class="docutils literal notranslate"><span class="pre"><index></span></code> is a 32-bit unsigned integer and <code class="docutils literal notranslate"><span class="pre">blocks</span></code> contains a list of <a class="reference internal" href="#block-references"><span class="std std-ref">machine basic block references</span></a>.</p>
<p>Example:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>jumpTable:
kind: inline
entries:
- id: 0
blocks: [ '%bb.3', '%bb.9', '%bb.4.d3' ]
- id: 1
blocks: [ '%bb.7', '%bb.7', '%bb.4.d3', '%bb.5' ]
</pre></div>
</div>
</div>
<div class="section" id="external-symbol-operands">
<h4><a class="toc-backref" href="#id38">External Symbol Operands</a><a class="headerlink" href="#external-symbol-operands" title="Permalink to this headline">¶</a></h4>
<p>An external symbol operand is represented using an identifier with the <code class="docutils literal notranslate"><span class="pre">&</span></code>
prefix. The identifier is surrounded with ““‘s and escaped if it has any
special non-printable characters in it.</p>
<p>Example:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
</pre></div>
</div>
</div>
<div class="section" id="mcsymbol-operands">
<h4><a class="toc-backref" href="#id39">MCSymbol Operands</a><a class="headerlink" href="#mcsymbol-operands" title="Permalink to this headline">¶</a></h4>
<p>A MCSymbol operand is holding a pointer to a <code class="docutils literal notranslate"><span class="pre">MCSymbol</span></code>. For the limitations
of this operand in MIR, see <a class="reference internal" href="#limitations"><span class="std std-ref">limitations</span></a>.</p>
<p>The syntax is:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>EH_LABEL <mcsymbol Ltmp1>
</pre></div>
</div>
</div>
<div class="section" id="cfiindex-operands">
<h4><a class="toc-backref" href="#id40">CFIIndex Operands</a><a class="headerlink" href="#cfiindex-operands" title="Permalink to this headline">¶</a></h4>
<p>A CFI Index operand is holding an index into a per-function side-table,
<code class="docutils literal notranslate"><span class="pre">MachineFunction::getFrameInstructions()</span></code>, which references all the frame
instructions in a <code class="docutils literal notranslate"><span class="pre">MachineFunction</span></code>. A <code class="docutils literal notranslate"><span class="pre">CFI_INSTRUCTION</span></code> may look like it
contains multiple operands, but the only operand it contains is the CFI Index.
The other operands are tracked by the <code class="docutils literal notranslate"><span class="pre">MCCFIInstruction</span></code> object.</p>
<p>The syntax is:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>CFI_INSTRUCTION offset $w30, -16
</pre></div>
</div>
<p>which may be emitted later in the MC layer as:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>.cfi_offset w30, -16
</pre></div>
</div>
</div>
<div class="section" id="intrinsicid-operands">
<h4><a class="toc-backref" href="#id41">IntrinsicID Operands</a><a class="headerlink" href="#intrinsicid-operands" title="Permalink to this headline">¶</a></h4>
<p>An Intrinsic ID operand contains a generic intrinsic ID or a target-specific ID.</p>
<p>The syntax for the <code class="docutils literal notranslate"><span class="pre">returnaddress</span></code> intrinsic is:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>$x0 = COPY intrinsic(@llvm.returnaddress)
</pre></div>
</div>
</div>
<div class="section" id="predicate-operands">
<h4><a class="toc-backref" href="#id42">Predicate Operands</a><a class="headerlink" href="#predicate-operands" title="Permalink to this headline">¶</a></h4>
<p>A Predicate operand contains an IR predicate from <code class="docutils literal notranslate"><span class="pre">CmpInst::Predicate</span></code>, like
<code class="docutils literal notranslate"><span class="pre">ICMP_EQ</span></code>, etc.</p>
<p>For an int eq predicate <code class="docutils literal notranslate"><span class="pre">ICMP_EQ</span></code>, the syntax is:</p>
<div class="highlight-text notranslate"><div class="highlight"><pre><span></span>%2:gpr(s32) = G_ICMP intpred(eq), %0, %1
</pre></div>
</div>
</div>
</div>
</div>
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