.TH "Device Structs" 3 "24 Apr 2019" "Version 1.1" "NVML" \" -*- nroff -*-
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.nh
.SH NAME
Device Structs \- 
.SS "Data Structures"

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.RI "struct \fBnvmlPciInfo_t\fP"
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.RI "struct \fBnvmlEccErrorCounts_t\fP"
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.RI "struct \fBnvmlUtilization_t\fP"
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.RI "struct \fBnvmlMemory_t\fP"
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.RI "struct \fBnvmlBAR1Memory_t\fP"
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.RI "struct \fBnvmlProcessInfo_t\fP"
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.RI "struct \fBnvmlNvLinkUtilizationControl_t\fP"
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.RI "struct \fBnvmlBridgeChipInfo_t\fP"
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.RI "struct \fBnvmlBridgeChipHierarchy_t\fP"
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.RI "union \fBnvmlValue_t\fP"
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.RI "struct \fBnvmlSample_t\fP"
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.RI "struct \fBnvmlViolationTime_t\fP"
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.SS "Defines"

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.RI "#define \fBNVML_VALUE_NOT_AVAILABLE\fP   (-1)"
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.RI "#define \fBNVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE\fP   32"
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.RI "#define \fBNVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE\fP   16"
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.RI "#define \fBNVML_DEVICE_PCI_BUS_ID_LEGACY_FMT\fP   '%04X:%02X:%02X.0'"
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.RI "#define \fBNVML_DEVICE_PCI_BUS_ID_FMT\fP   '%08X:%02X:%02X.0'"
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.RI "#define \fBNVML_DEVICE_PCI_BUS_ID_FMT_ARGS\fP(pciInfo)"
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.RI "#define \fBNVML_NVLINK_MAX_LINKS\fP   6"
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.RI "#define \fBNVML_MAX_PHYSICAL_BRIDGE\fP   (128)"
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.SS "Enumerations"

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.RI "enum \fBnvmlBridgeChipType_t\fP "
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.RI "enum \fBnvmlNvLinkUtilizationCountUnits_t\fP "
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.RI "enum \fBnvmlNvLinkUtilizationCountPktTypes_t\fP "
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.RI "enum \fBnvmlNvLinkCapability_t\fP "
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.RI "enum \fBnvmlNvLinkErrorCounter_t\fP "
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.RI "enum \fBnvmlGpuTopologyLevel_t\fP "
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.RI "enum \fBnvmlSamplingType_t\fP { \fBNVML_TOTAL_POWER_SAMPLES\fP =  0, \fBNVML_GPU_UTILIZATION_SAMPLES\fP =  1, \fBNVML_MEMORY_UTILIZATION_SAMPLES\fP =  2, \fBNVML_ENC_UTILIZATION_SAMPLES\fP =  3, \fBNVML_DEC_UTILIZATION_SAMPLES\fP =  4, \fBNVML_PROCESSOR_CLK_SAMPLES\fP =  5, \fBNVML_MEMORY_CLK_SAMPLES\fP =  6 }"
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.RI "enum \fBnvmlPcieUtilCounter_t\fP "
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.RI "enum \fBnvmlValueType_t\fP "
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.RI "enum \fBnvmlPerfPolicyType_t\fP { \fBNVML_PERF_POLICY_POWER\fP =  0, \fBNVML_PERF_POLICY_THERMAL\fP =  1, \fBNVML_PERF_POLICY_SYNC_BOOST\fP =  2, \fBNVML_PERF_POLICY_BOARD_LIMIT\fP =  3, \fBNVML_PERF_POLICY_LOW_UTILIZATION\fP =  4, \fBNVML_PERF_POLICY_RELIABILITY\fP =  5, \fBNVML_PERF_POLICY_TOTAL_APP_CLOCKS\fP =  10, \fBNVML_PERF_POLICY_TOTAL_BASE_CLOCKS\fP =  11 }"
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.SH "Define Documentation"
.PP 
.SS "#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE   32"
.PP
Buffer size guaranteed to be large enough for pci bus id 
.SS "#define NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE   16"
.PP
Buffer size guaranteed to be large enough for pci bus id for busIdLegacy 
.SS "#define NVML_DEVICE_PCI_BUS_ID_FMT   '%08X:%02X:%02X.0'"
.PP
PCI format string for busId 
.SS "#define NVML_DEVICE_PCI_BUS_ID_FMT_ARGS(pciInfo)"
.PP
\fBValue:\fP
.PP
.nf
(pciInfo)->domain, \
                                                    (pciInfo)->bus,    \
                                                    (pciInfo)->device
.fi
Utility macro for filling the pci bus id format from a \fBnvmlPciInfo_t\fP 
.SS "#define NVML_DEVICE_PCI_BUS_ID_LEGACY_FMT   '%04X:%02X:%02X.0'"
.PP
PCI format string for busIdLegacy 
.SS "#define NVML_MAX_PHYSICAL_BRIDGE   (128)"
.PP
Maximum limit on Physical Bridges per Board 
.SS "#define NVML_NVLINK_MAX_LINKS   6"
.PP
Maximum number of NvLink links supported 
.SS "#define NVML_VALUE_NOT_AVAILABLE   (-1)"
.PP
Special constant that some fields take when they are not available. Used when only part of the struct is not available.
.PP
Each structure explicitly states when to check for this value. 
.SH "Enumeration Type Documentation"
.PP 
.SS "enum \fBnvmlBridgeChipType_t\fP"
.PP
Enum to represent type of bridge chip 
.SS "enum \fBnvmlGpuTopologyLevel_t\fP"
.PP
Represents level relationships within a system between two GPUs The enums are spaced to allow for future relationships 
.SS "enum \fBnvmlNvLinkCapability_t\fP"
.PP
Enum to represent NvLink queryable capabilities 
.SS "enum \fBnvmlNvLinkErrorCounter_t\fP"
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Enum to represent NvLink queryable error counters 
.SS "enum \fBnvmlNvLinkUtilizationCountPktTypes_t\fP"
.PP
Enum to represent the NvLink utilization counter packet types to count ** this is ONLY applicable with the units as packets or bytes ** as specified in \fInvmlNvLinkUtilizationCountUnits_t\fP ** all packet filter descriptions are target GPU centric ** these can be 'OR'd' together 
.SS "enum \fBnvmlNvLinkUtilizationCountUnits_t\fP"
.PP
Enum to represent the NvLink utilization counter packet units 
.SS "enum \fBnvmlPcieUtilCounter_t\fP"
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Represents the queryable PCIe utilization counters 
.SS "enum \fBnvmlPerfPolicyType_t\fP"
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Represents type of perf policy for which violation times can be queried 
.PP
\fBEnumerator: \fP
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.TP
\fB\fINVML_PERF_POLICY_POWER \fP\fP
How long did power violations cause the GPU to be below application clocks. 
.TP
\fB\fINVML_PERF_POLICY_THERMAL \fP\fP
How long did thermal violations cause the GPU to be below application clocks. 
.TP
\fB\fINVML_PERF_POLICY_SYNC_BOOST \fP\fP
How long did sync boost cause the GPU to be below application clocks. 
.TP
\fB\fINVML_PERF_POLICY_BOARD_LIMIT \fP\fP
How long did the board limit cause the GPU to be below application clocks. 
.TP
\fB\fINVML_PERF_POLICY_LOW_UTILIZATION \fP\fP
How long did low utilization cause the GPU to be below application clocks. 
.TP
\fB\fINVML_PERF_POLICY_RELIABILITY \fP\fP
How long did the board reliability limit cause the GPU to be below application clocks. 
.TP
\fB\fINVML_PERF_POLICY_TOTAL_APP_CLOCKS \fP\fP
Total time the GPU was held below application clocks by any limiter (0 - 5 above). 
.TP
\fB\fINVML_PERF_POLICY_TOTAL_BASE_CLOCKS \fP\fP
Total time the GPU was held below base clocks. 
.SS "enum \fBnvmlSamplingType_t\fP"
.PP
Represents Type of Sampling Event 
.PP
\fBEnumerator: \fP
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.TP
\fB\fINVML_TOTAL_POWER_SAMPLES \fP\fP
To represent total power drawn by GPU. 
.TP
\fB\fINVML_GPU_UTILIZATION_SAMPLES \fP\fP
To represent percent of time during which one or more kernels was executing on the GPU. 
.TP
\fB\fINVML_MEMORY_UTILIZATION_SAMPLES \fP\fP
To represent percent of time during which global (device) memory was being read or written. 
.TP
\fB\fINVML_ENC_UTILIZATION_SAMPLES \fP\fP
To represent percent of time during which NVENC remains busy. 
.TP
\fB\fINVML_DEC_UTILIZATION_SAMPLES \fP\fP
To represent percent of time during which NVDEC remains busy. 
.TP
\fB\fINVML_PROCESSOR_CLK_SAMPLES \fP\fP
To represent processor clock samples. 
.TP
\fB\fINVML_MEMORY_CLK_SAMPLES \fP\fP
To represent memory clock samples. 
.SS "enum \fBnvmlValueType_t\fP"
.PP
Represents the type for sample value returned 
.SH "Author"
.PP 
Generated automatically by Doxygen for NVML from the source code.